[S] Change in coreboot[master]: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750

[Kun Liu (Code Review)]

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76912?usp=email )

Change subject: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
......................................................................

mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750

Compatible with RTS5227S and GL9750

BUG=b:284273384
TEST=emerge-rex coreboot

Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8
Signed-off-by: Kun Liu 
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/76912/1

diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index a7b7d54..9320011 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -18,6 +18,11 @@
    	option TOUCHSCREEN_ILITEK	1
    	option TOUCHSCREEN_ELAN		2
    end
+	field DB_SD 11 12
+		option SD_ABSENT 0
+		option SD_GL9750 1
+		option SD_RTS5227S 2
+	end
 end

chip soc/intel/meteorlake
@@ -251,7 +256,10 @@
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
    			register "srcclk_pin" = "7"
-				device generic 0 on end
+				device generic 0 on
+					probe DB_SD SD_GL9750
+					probe DB_SD SD_RTS5227S
+				end
    		end
    	end
    	device ref tbt_pcie_rp0 on end