Change in coreboot[master]: soc/intel/jasperlake: Disable multiphase SI init

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43816 )

Change subject: soc/intel/jasperlake: Disable multiphase SI init
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soc/intel/jasperlake: Disable multiphase SI init

Jasper Lake does not have any use case for multiphase SI init so
Disable it.

BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP

Cq-Depend: chrome-internal:3221772
Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e
Signed-off-by: Ronak Kanabar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43816
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Aamir Bohra 
Reviewed-by: Maulik V Vaghela 
---
M src/soc/intel/jasperlake/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aamir Bohra: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index c45af27..40be0d4 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -349,6 +349,12 @@
    mainboard_silicon_init_params(params);
 }

+/* Disable Multiphase Si init */
+int soc_fsp_multi_phase_init_is_enable(void)
+{
+	return 0;
+}
+
 /* Mainboard GPIO Configuration */
 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {