[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email )

Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................

mb/google/fatcat: Limit Power Limit when battery is missing

Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case.

BUG=b:377798581
TEST=See power limit override log message when the battery is missing
     on fatcat board

Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e
Signed-off-by: Jeremy Compostella 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85146
Reviewed-by: Dinesh Gehlot 
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
A src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
3 files changed, 34 insertions(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index e4c98dd..37ba330 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -32,6 +32,7 @@
    select MAINBOARD_HAS_TPM2
    select MB_COMPRESS_RAMSTAGE_LZ4
    select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
    select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
    select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
    select SOC_INTEL_PANTHERLAKE_U_H
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
index be05cd4..47123cd 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk
@@ -1,3 +1,4 @@
 ## SPDX-License-Identifier: GPL-2.0-only

romstage-y += memory.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
new file mode 100644
index 0000000..4b9cfd2
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ */
+const struct cpu_tdp_power_limits power_optimized_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
+		.cpu_tdp = 25,
+		.power_limits_index = PTL_H_1_CORE,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 25000,
+		.pl2_min_power = 50000,
+		.pl2_max_power = 50000,
+		.pl4_power = 50000 /* TODO: needs fine tuning */
+	},
+};
+
+void baseboard_devtree_update(void)
+{
+	/* Don't optimize the power limit if booting with barrel attached */
+	if (google_chromeec_is_barrel_charger_present())
+		return;
+
+	if (!google_chromeec_is_battery_present())
+		variant_update_cpu_power_limits(power_optimized_limits,
+						ARRAY_SIZE(power_optimized_limits));
+}