[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines - coreboot-gerrit

12 Sep 2024


      Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )
Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 4:
(1 comment)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/56fca2dd_35810639?usp... :
PS4, Line 30: 146
...
unable to follow why the index is 145 or 0x91 ? […]
GPE1[0] starts from 0x80 (i.e. 128 dec) CNVI_BT_PME_B0 is bit 18, 128 + 18 = 146 (0x92), corresponding to _L92 events.
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Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
Gerrit-Change-Number: 84297
Gerrit-PatchSet: 4
Gerrit-Owner: Cliff Huang cliff.huang@intel.com
Gerrit-Reviewer: Kapil Porwal kapilporwal@google.com
Gerrit-Reviewer: Pranava Y N pranavayn@google.com
Gerrit-Reviewer: Subrata Banik subratabanik@google.com
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