[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Ravishankar Sarawadi, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
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Patch Set 67:

(10 comments)

File src/soc/intel/pantherlake/chipset.cb:

https://review.coreboot.org/c/coreboot/+/83635/comment/44e651c8_c899d55d?usp... :
PS64, Line 17: off
> `on` may be ?

It is not enabled in n-1 platform, is it req. to be enabled?

https://review.coreboot.org/c/coreboot/+/83635/comment/c42b1e73_e847f788?usp... :
PS64, Line 48: 		device pci 08.0 alias gna off end
> i don't see this device listed inside PTL EDS 815002

Ack, Removing.

https://review.coreboot.org/c/coreboot/+/83635/comment/acfdf8d4_129aecde?usp... :
PS64, Line 49: off
> want to keep crashlog `on` ?

Yes, keeping crashlog on

https://review.coreboot.org/c/coreboot/+/83635/comment/9d49e9fb_183929c2?usp... :
PS64, Line 65: 				end
> Please add […]

Acknowledged

File src/soc/intel/pantherlake/include/soc/romstage.h:

https://review.coreboot.org/c/coreboot/+/83635/comment/f3b39d15_bebe886f?usp... :
PS66, Line 12: soc_die
> `pcd` that is what you have done in bootblock ? […]

There's no user outside of bootblock/pcd.c
Ack,removing.

https://review.coreboot.org/c/coreboot/+/83635/comment/93867fc3_4b0adfea?usp... :
PS66, Line 14:
> please use […]

Acknowledged

File src/soc/intel/pantherlake/p2sb.c:

https://review.coreboot.org/c/coreboot/+/83635/comment/e10eb5bc_2424e6de?usp... :
PS64, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> please add this file as part of the ramstage CL as there is no consumer of p2sb. […]

Acknowledged

File src/soc/intel/pantherlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/83635/comment/906c0730_9bf19223?usp... :
PS64, Line 36: 		timestamp_add_now(TS_CSE_FW_SYNC_START);
> we have added these timestamp inside `cse_fw_sync` hence, please drop […]

Sure. Ack.

https://review.coreboot.org/c/coreboot/+/83635/comment/101d9b2c_24cb5e2b?usp... :
PS64, Line 37: 		cse_fw_sync();
> why are you enforcing CSE sync in romstage ? […]

Followed MTL.

https://review.coreboot.org/c/coreboot/+/83635/comment/46dbb5ff_f6b69307?usp... :
PS64, Line 40:
> missing  […]

Ack, Added.