HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46163 )
Change subject: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax ......................................................................
mb/emulation/qemu-q35: Convert to ASL 2.0 syntax
Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/emulation/qemu-q35/dsdt.asl 1 file changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46163/1
diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a9c96be..274cccb 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -45,31 +45,31 @@ CreateDWordField(Arg3, 0, CDW1)
// Check for proper UUID - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { // Create DWORD-addressable fields from the Capabilities Buffer CreateDWordField(Arg3, 4, CDW2) CreateDWordField(Arg3, 8, CDW3)
// Save Capabilities DWORD2 & 3 - Store(CDW2, SUPP) - Store(CDW3, CTRL) + SUPP = CDW2 + CTRL = CDW3
// Always allow native PME, AER (no dependencies) // Never allow SHPC (no SHPC controller in this system) - And(CTRL, 0x1D, CTRL) + CTRL &= 0x1D
- If (LNotEqual(Arg1, One)) { + If (Arg1 != 1) { // Unknown revision - Or(CDW1, 0x08, CDW1) + CDW1 |= 0x08 } - If (LNotEqual(CDW3, CTRL)) { + If (CDW3 != CTRL) { // Capabilities bits were masked - Or(CDW1, 0x10, CDW1) + CDW1 |= 0x10 } // Update DWORD3 in the buffer - Store(CTRL, CDW3) + CDW3 = CTRL } Else { - Or(CDW1, 4, CDW1) // Unrecognized UUID + CDW1 |= 4 // Unrecognized UUID } Return (Arg3) } @@ -144,7 +144,7 @@ /* Zero => PIC mode, One => APIC Mode */ Name(\PICF, Zero) Method(_PIC, 1, NotSerialized) { - Store(Arg0, \PICF) + \PICF = Arg0 }
Scope(_SB) { @@ -268,7 +268,7 @@ section 6.2.8.1 */ /* Note: we provide the same info as the PCI routing table of the Bochs BIOS */ - If (LEqual(\PICF, Zero)) { + If (\PICF == 0) { Return (PRTP) } Else { Return (PRTA) @@ -291,7 +291,7 @@
Method(IQST, 1, NotSerialized) { // _STA method - get status - If (And(0x80, Arg0)) { + If (0x80 & Arg0) { Return (0x09) } Return (0x0B) @@ -302,7 +302,7 @@ Interrupt(, Level, ActiveHigh, Shared) { 0 } }) CreateDWordField(PRR0, 0x05, PRRI) - Store(And(Arg0, 0x0F), PRRI) + PRRI = Arg0 & 0x0F Return (PRR0) }
@@ -319,14 +319,14 @@ Return (IQST(reg)) \ } \ Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ + reg |= 0x80 \ } \ Method(_CRS, 0, NotSerialized) { \ Return (IQCR(reg)) \ } \ Method(_SRS, 1, NotSerialized) { \ CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ + reg = PRRI \ } \ }
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46163
to look at the new patch set (#2).
Change subject: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax ......................................................................
mb/emulation/qemu-q35: Convert to ASL 2.0 syntax
Generated 'build/sddt.dsl' files are identical.
Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/emulation/qemu-q35/dsdt.asl 1 file changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46163/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46163
to look at the new patch set (#3).
Change subject: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax ......................................................................
mb/emulation/qemu-q35: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.
Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/emulation/qemu-q35/dsdt.asl 1 file changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46163/3
Attention is currently required from: HAOUAS Elyes. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46163 )
Change subject: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46163 )
Change subject: mb/emulation/qemu-q35: Convert to ASL 2.0 syntax ......................................................................
mb/emulation/qemu-q35: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.
Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/emulation/qemu-q35/dsdt.asl 1 file changed, 16 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 494e296..3a9e571 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -46,31 +46,31 @@ CreateDWordField(Arg3, 0, CDW1)
// Check for proper UUID - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { // Create DWORD-addressable fields from the Capabilities Buffer CreateDWordField(Arg3, 4, CDW2) CreateDWordField(Arg3, 8, CDW3)
// Save Capabilities DWORD2 & 3 - Store(CDW2, SUPP) - Store(CDW3, CTRL) + SUPP = CDW2 + CTRL = CDW3
// Always allow native PME, AER (no dependencies) // Never allow SHPC (no SHPC controller in this system) - And(CTRL, 0x1D, CTRL) + CTRL &= 0x1D
- If (LNotEqual(Arg1, One)) { + If (Arg1 != 1) { // Unknown revision - Or(CDW1, 0x08, CDW1) + CDW1 |= 0x08 } - If (LNotEqual(CDW3, CTRL)) { + If (CDW3 != CTRL) { // Capabilities bits were masked - Or(CDW1, 0x10, CDW1) + CDW1 |= 0x10 } // Update DWORD3 in the buffer - Store(CTRL, CDW3) + CDW3 = CTRL } Else { - Or(CDW1, 4, CDW1) // Unrecognized UUID + CDW1 |= 4 // Unrecognized UUID } Return (Arg3) } @@ -145,7 +145,7 @@ /* Zero => PIC mode, One => APIC Mode */ Name(\PICF, Zero) Method(_PIC, 1, NotSerialized) { - Store(Arg0, \PICF) + \PICF = Arg0 }
Scope(_SB) { @@ -269,7 +269,7 @@ section 6.2.8.1 */ /* Note: we provide the same info as the PCI routing table of the Bochs BIOS */ - If (LEqual(\PICF, Zero)) { + If (\PICF == 0) { Return (PRTP) } Else { Return (PRTA) @@ -292,7 +292,7 @@
Method(IQST, 1, NotSerialized) { // _STA method - get status - If (And(0x80, Arg0)) { + If (0x80 & Arg0) { Return (0x09) } Return (0x0B) @@ -303,7 +303,7 @@ Interrupt(, Level, ActiveHigh, Shared) { 0 } }) CreateDWordField(PRR0, 0x05, PRRI) - Store(And(Arg0, 0x0F), PRRI) + PRRI = Arg0 & 0x0F Return (PRR0) }
@@ -320,14 +320,14 @@ Return (IQST(reg)) \ } \ Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ + reg |= 0x80 \ } \ Method(_CRS, 0, NotSerialized) { \ Return (IQCR(reg)) \ } \ Method(_SRS, 1, NotSerialized) { \ CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ + reg = PRRI \ } \ }
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)