Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84349?usp=email )
Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI ......................................................................
soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0'
BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method.
Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349 Reviewed-by: Subrata Banik subratabanik@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 51b0e23..dd176e6 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -291,12 +291,12 @@ * B0:D0:F0:Reg.48h */ Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB) - +#if DMI_BASE_SIZE /* DMI BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.68h */ Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB) - +#endif /* EP BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.40h */ @@ -322,10 +322,10 @@
CreateDwordField (BUF0, MCHB._BAS, MBR0) MBR0 = _SB.PCI0.GMHB () - +#if DMI_BASE_SIZE CreateDwordField (BUF0, DMIB._BAS, DBR0) DBR0 = _SB.PCI0.GDMB () - +#endif CreateDwordField (BUF0, EGPB._BAS, EBR0) EBR0 = _SB.PCI0.GEPB ()