[M] Change in coreboot[main]: soc/intel/alderlake: Add a function to force disable memory channels

[Jamie Chen (Code Review)]

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford.

Jamie Chen has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email )

Change subject: soc/intel/alderlake: Add a function to force disable memory channels
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/85529/comment/ebd0f09f_3784ce63?usp... :
PS1, Line 252: 	if (ch_disable_mask == 0) {
> I need to check the answer internally, will reply later.

Per intel PDG doc "LPDDR5 x32 memory down placement and block diagram", MC0CH0/MC0CH1 enabled or MC0CH2/MC0CH3 enabled is valid case based on DRAM chip population, but correctly for one dram chip to support x32 we only do the validation on MC0Ch0/MC0Ch1 enabled.
Could we add a message to suggest using MC0Ch0/MC0Ch1 combination for x32 memory configuration?