Attention is currently required from: Sridhar Siricilla, Paul Menzel, Ravindra, Patrick Rudolph. Hello build bot (Jenkins), Sridhar Siricilla, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55363
to look at the new patch set (#8).
Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver ......................................................................
soc/intel/common: Add HECI Reset flow in the CSE driver
This change is required as part of HECI Interface initialization in order to put the host and CSE into a known good state for communication. Please refer ME BIOS specification for more details. The change adds HECI interface reset flow in the CSE driver. It enables coreboot to send HECI commands before DRAM Init.
TEST=Run 50 cold reset cycles on Brya
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55363/8