Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76037?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for PchUnlockGpioPads dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for PchUnlockGpioPads dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="PchUnlockGpioPads" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: Iccffbbb0e2ce773af11b949ba6f35660341e8cf2 Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/76037/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e266c43..c83ce0c 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -35,7 +35,7 @@ register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s - register "PchUnlockGpioPads" = "1" + register PchUnlockGpioPads = true # USB2 PHY Power gating register PchUsb2PhySusPgDisable = true
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 56926f3..cd5506d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -43,7 +43,7 @@ register DdiPortCHpd = true register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads - register "PchUnlockGpioPads" = "1" + register PchUnlockGpioPads = true # SD card WP pin configuration register ScsSdCardWpPinEnabled = false
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 1240333..fee9707 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -43,7 +43,7 @@ register DdiPortCHpd = true register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads - register "PchUnlockGpioPads" = "1" + register PchUnlockGpioPads = true # SD card WP pin configuration register ScsSdCardWpPinEnabled = false
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 734d6f2..cde96fb 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -23,7 +23,7 @@ register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s - register "PchUnlockGpioPads" = "1" + register PchUnlockGpioPads = true # USB2 PHY Power gating register PchUsb2PhySusPgDisable = true
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 395e2a1..6218c81 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -10,7 +10,7 @@ register "gen4_dec" = "0x001c02e1"
# GPIO - register "PchUnlockGpioPads" = "1" + register PchUnlockGpioPads = true register "gpe0_dw0" = "0x2" register "gpe0_dw1" = "0x3" register "gpe0_dw2" = "0xd"