Change in ...coreboot[master]: arch/riscv: Don't hardcode CSR numbers anymore

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30164

Change subject: arch/riscv: Don't hardcode CSR numbers anymore
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arch/riscv: Don't hardcode CSR numbers anymore

They are hopefully stable enough by now.

TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS,
     with and without this patch, results in the same coreboot.rom.

Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038
Signed-off-by: Jonathan Neuschäfer 
---
M src/arch/riscv/virtual_memory.c
1 file changed, 2 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30164/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index d9bae2a..0061847 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -59,11 +59,6 @@
    	set_csr(medeleg, delegate);
    }

-	// Enable all user/supervisor-mode counters using
-	// v1.10 register addresses.
-	// They moved from the earlier spec.
-	// Until we trust our toolchain use the hardcoded constants.
-	// These were in flux and people who get the older toolchain
-	// will have difficult-to-debug failures.
-	write_csr(/*mcounteren*/0x306, 7);
+	// Enable all user/supervisor-mode counters
+	write_csr(mcounteren, 7);
 }