Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83316?usp=email )
(
10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos ......................................................................
soc/intel/common/block/gpio/gpio.c: Improve GPIO debug infos
1. print host software ownership, SMI enable and NMI enable registers after configuring 2. read and print GPIO configuration dword registers after writing 3. use %zu to print size_t values according to CI reporting.
Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5 Signed-off-by: Yuchi Chen yuchi.chen@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316 Reviewed-by: Shuo Liu shuo.liu@intel.com Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 28 insertions(+), 9 deletions(-)
Approvals: Jérémy Compostella: Looks good to me, but someone else must approve build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 63d7a5e..d49742d 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -167,6 +167,12 @@ hostsw_own &= ~gpio_bitmask_within_group(comm, pin);
pcr_write32(comm->port, hostsw_own_offset, hostsw_own); + + if (CONFIG(DEBUG_GPIO)) { + printk(BIOS_DEBUG, "HOST_OWN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), hostsw_own_offset, + pcr_read32(comm->port, hostsw_own_offset)); + } }
static void gpi_enable_gpe(const struct pad_config *cfg, @@ -187,7 +193,7 @@ pcr_or32(comm->port, en_reg, en_value);
if (CONFIG(DEBUG_GPIO)) { - printk(BIOS_DEBUG, "GPE_EN[0x%02x, %02zd]: Reg: 0x%x, Value = 0x%x\n", + printk(BIOS_DEBUG, "GPE_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", comm->port, relative_pad_in_comm(comm, cfg->pad), en_reg, pcr_read32(comm->port, en_reg)); } @@ -212,6 +218,12 @@
/* Set enable bits */ pcr_or32(comm->port, en_reg, en_value); + + if (CONFIG(DEBUG_GPIO)) { + printk(BIOS_DEBUG, "SMI_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), en_reg, + pcr_read32(comm->port, en_reg)); + } }
static void gpi_enable_nmi(const struct pad_config *cfg, @@ -237,6 +249,12 @@
/* Set enable bits */ pcr_or32(comm->port, en_reg, en_value); + + if (CONFIG(DEBUG_GPIO)) { + printk(BIOS_DEBUG, "NMI_EN[0x%02x, %02zu]: Reg: 0x%x, Value = 0x%08x\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), en_reg, + pcr_read32(comm->port, en_reg)); + } }
/* 120 GSIs is the default for IOxAPIC */ @@ -368,16 +386,17 @@ /* Patch GPIO settings for SoC specifically */ soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
- if (CONFIG(DEBUG_GPIO)) - printk(BIOS_DEBUG, - "gpio_padcfg [0x%02x, %02d] DW%d [0x%08x : 0x%08x" - " : 0x%08x]\n", - comm->port, pin, i, - pad_conf,/* old value */ - cfg->pad_config[i],/* value passed from gpio table */ - soc_pad_conf);/*new value*/ pcr_write32(comm->port, PAD_CFG_OFFSET(config_offset, i), soc_pad_conf); + + if (CONFIG(DEBUG_GPIO)) + printk(BIOS_DEBUG, + "gpio_padcfg [0x%02x, %02d] DW%d [0x%08x : 0x%08x : 0x%08x : 0x%08x]\n", + comm->port, pin, i, + pad_conf, /* old value */ + cfg->pad_config[i], /* value passed from gpio table */ + soc_pad_conf, /* new value */ + pcr_read32(comm->port, PAD_CFG_OFFSET(config_offset, i))); /* updated value */ }
gpio_configure_itss(cfg, comm->port, config_offset);