[XL] Change in coreboot[main]: mb/lenovo: Add Thinkcentre M900 (Skylake/LGA 1151)

[Felix Singer (Code Review)]

Attention is currently required from: Alexander Couzens, Nicholas Chin, Paul Menzel.

Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email )

Change subject: mb/lenovo: Add Thinkcentre M900 (Skylake/LGA 1151)
......................................................................

Patch Set 2:

(6 comments)

File src/mainboard/lenovo/m900/Kconfig:

https://review.coreboot.org/c/coreboot/+/74187/comment/34ad520d_c14fda2f?usp... :
PS2, Line 1: if BOARD_LENOVO_M900
```suggestion
## SPDX-License-Identifier: GPL-2.0-only

if BOARD_LENOVO_M900
```

File src/mainboard/lenovo/m900/Kconfig.name:

https://review.coreboot.org/c/coreboot/+/74187/comment/94301ab8_f4390827?usp... :
PS2, Line 1: config BOARD_LENOVO_M900
```suggestion
## SPDX-License-Identifier: GPL-2.0-only

config BOARD_LENOVO_M900
```

File src/mainboard/lenovo/m900/Makefile.inc:

PS2: 
Rebase and rename to Makefile.mk

File src/mainboard/lenovo/m900/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/74187/comment/c3104671_de22c09e?usp... :
PS2, Line 53: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
            : 			register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
            : 			register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
            : 			register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
            : 			register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
            : 			register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
            : 			register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
            : 			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
```suggestion
    		register "usb2_ports" = "{
    			[0] = USB2_PORT_MID(OC0),
    			[1] = USB2_PORT_MID(OC0),
    			[2] = USB2_PORT_MID(OC4),
    			[3] = USB2_PORT_MID(OC4),
    			[4] = USB2_PORT_MID(OC2),
    			[5] = USB2_PORT_MID(OC2),
    			[6] = USB2_PORT_MID(OC0),
    			[7] = USB2_PORT_MID(OC0),
    			[8] = USB2_PORT_MID(OC0),
    			[9] = USB2_PORT_MID(OC0),
    			[10] = USB2_PORT_MID(OC1),
    			[11] = USB2_PORT_MID(OC1),
    			[12] = USB2_PORT_MID(OC_SKIP),
    			[13] = USB2_PORT_MID(OC_SKIP),
    		}"
```

https://review.coreboot.org/c/coreboot/+/74187/comment/f66af308_4872e667?usp... :
PS2, Line 68: 			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
            : 			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
            : 			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
            : 			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
            : 			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
            : 			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
            : 			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
            : 			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
            : 			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
            : 		
```suggestion
    		register "usb3_ports" = "{
    			[0] = USB3_PORT_DEFAULT(OC0),
    			[1] = USB3_PORT_DEFAULT(OC0),
    			[2] = USB3_PORT_DEFAULT(OC3),
    			[3] = USB3_PORT_DEFAULT(OC3),
    			[4] = USB3_PORT_DEFAULT(OC1),
    			[5] = USB3_PORT_DEFAULT(OC1),
    			[6] = USB3_PORT_DEFAULT(OC_SKIP),
    			[7] = USB3_PORT_DEFAULT(OC_SKIP),
    			[8] = USB3_PORT_DEFAULT(OC_SKIP),
    			[9] = USB3_PORT_DEFAULT(OC_SKIP),
    		}"
```

https://review.coreboot.org/c/coreboot/+/74187/comment/53dbcbe1_3d87a65b?usp... :
PS2, Line 97: register "SataPortsEnable" = "{ \
            : 				[0]     = 1, \
            : 				[1]     = 1, \
            : 				[2]     = 1, \
            : 				[3]     = 1, \
            : 			}"
The backslashes for line continuation are not needed

```suggestion
    		register "SataPortsEnable" = "{
    			[0]     = 1,
    			[1]     = 1,
    			[2]     = 1,
    			[3]     = 1,
    		}"
```