Change in coreboot[master]: soc/intel/broadwell/memmap.c: Use Haswell implementation

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46992 )

Change subject: soc/intel/broadwell/memmap.c: Use Haswell implementation
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soc/intel/broadwell/memmap.c: Use Haswell implementation

Change-Id: I0752418cdf0bf39241e1c798b7aeb1a8b137c6f8
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/memmap.c
1 file changed, 40 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46992/1

diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 8b1567e..7eb2d42 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -4,45 +4,66 @@
 #define __SIMPLE_DEVICE__

#include <arch/romstage.h>
-#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <device/pci.h>
 #include <device/pci_ops.h>
-#include <stdint.h>
+#include <cbmem.h>
+#include <security/intel/txt/txt_platform.h>
+#include <security/intel/txt/txt_register.h>
+#include <types.h>

#include "haswell.h"

-static uintptr_t dpr_region_start(void)
+static uintptr_t northbridge_get_tseg_base(void)
+{
+	return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB);
+}
+
+static uintptr_t northbridge_get_tseg_limit(void)
+{
+	return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB);
+}
+
+union dpr_register txt_get_chipset_dpr(void)
+{
+	return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) };
+}
+
+/*
+ * Return the topmost memory address below 4 GiB available for general
+ * use, from software's view of memory. Do not confuse this with TOLUD,
+ * which applies to the DRAM as viewed by the memory controller itself.
+ */
+static uintptr_t top_of_low_usable_memory(void)
 {
    /*
-	 * Base of DPR is top of usable DRAM below 4GiB. The register has
-	 * 1 MiB alignment and reports the TOP of the range, the base
-	 * must be calculated from the size in MiB in bits 11:4.
+	 * Base of DPR is top of usable DRAM below 4 GiB. However, DPR
+	 * isn't always enabled. Unlike most memory map registers, the
+	 * DPR register stores top of DPR instead of its base address.
+	 * Top of DPR is R/O, and mirrored from TSEG base by hardware.
     */
-	uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR);
-	uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);
+	uintptr_t tolum = northbridge_get_tseg_base();
+
+	const union dpr_register dpr = txt_get_chipset_dpr();

/* Subtract DMA Protected Range size if enabled */
-	if (dpr & DPR_EPM)
-		tom -= (dpr & DPR_SIZE_MASK) << 16;
+	if (dpr.epm)
+		tolum -= dpr.size * MiB;

-	return tom;
+	return tolum;
 }

void *cbmem_top_chipset(void)
 {
-	return (void *) dpr_region_start();
+	return (void *)top_of_low_usable_memory();
 }

void smm_region(uintptr_t *start, size_t *size)
 {
-	uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG);
-	uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_limit();

-	tseg = ALIGN_DOWN(tseg, 1 * MiB);
-	bgsm = ALIGN_DOWN(bgsm, 1 * MiB);
-	*start = tseg;
-	*size = bgsm - tseg;
+	*size -= *start;
 }

void fill_postcar_frame(struct postcar_frame *pcf)

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46992 )

Change subject: soc/intel/broadwell/memmap.c: Use Haswell implementation
......................................................................

Abandoned