Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
mb/foxconn/d41s/devicetree.cb: Indent with tabs
As on most other boards, use tabs to indent the devicetree.
Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/foxconn/d41s/devicetree.cb 1 file changed, 92 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38075/1
diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 19d3e10..06d871a 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -1,8 +1,8 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit damien@zamaudio.com -# Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -11,102 +11,101 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. #
chip northbridge/intel/pineview # Northbridge - register "gfx.use_spread_spectrum_clock" = "0" - register "use_crt" = "1" - register "use_lvds" = "0" + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0"
- device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - subsystemid 0x105b 0x0d55 inherit - device pci 0.0 on end # Host Bridge - device pci 1.0 off end # PEG - device pci 2.0 on end # Integrated graphics controller - device pci 2.1 off end # Integrated graphics controller 2 - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x441" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FCBGA559 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + subsystemid 0x105b 0x0d55 inherit + device pci 0.0 on end # Host Bridge + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 off end # Integrated graphics controller 2
- register "gen1_dec" = "0x00fc0a01" # Environment Controller + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x441"
- device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2 (NIC) - device pci 00.0 on end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1d.0 on end # USB - device pci 1d.1 on end # USB - device pci 1d.2 on end # USB - device pci 1d.3 on end # USB - device pci 1d.7 on end # USB - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio (not on nm10?) - #device pci 1e.3 off end # AC'97 Modem (not on nm10?) - device pci 1f.0 on # ISA bridge - chip superio/ite/it8721f # Super I/O - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # PP - io 0x60 = 0x378 - io 0x62 = 0 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0xa10 - io 0x62 = 0xa00 - irq 0x70 = 0 - end - device pnp 2e.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.a on # CIR - io 0x60 = 0x3e0 - irq 0x70 = 10 - end - end - end - device pci 1f.1 off end # PATA - device pci 1f.2 on end # SATA - device pci 1f.3 on # SMbus - chip drivers/i2c/ck505 - register "mask" = "{ 0x00, 0x80, 0xff, 0xff, - 0xff }" - register "regs" = "{ 0x00, 0x80, 0xfe, 0xff, - 0xfc }" - device i2c 69 on end - end - end - end - end + register "gen1_dec" = "0x00fc0a01" # Environment Controller + + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio (not on nm10?) + #device pci 1e.3 off end # AC'97 Modem (not on nm10?) + device pci 1f.0 on # ISA bridge + chip superio/ite/it8721f # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # PP + io 0x60 = 0x378 + io 0x62 = 0 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0 + end + device pnp 2e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a on # CIR + io 0x60 = 0x3e0 + irq 0x70 = 10 + end + end + end + device pci 1f.1 off end # PATA + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 + register "mask" = "{ 0x00, 0x80, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x00, 0x80, 0xfe, 0xff, 0xfc }" + device i2c 69 on end + end + end + end + end end
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... File src/mainboard/foxconn/d41s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... PS1, Line 4: # Copyright (C) 2015 Damien Zammit damien@zamaudio.com : # Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz : # : # This program is free software; you can redistribute it and/or modify : # it under the terms of the GNU General Public License as published by : # the Free Software Foundation; either version 2 of the License, or : # (at your option) any later version. : # : # This program is distributed in the hope that it will be useful, : # but WITHOUT ANY WARRANTY; without even the implied warranty of : # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the Too much automatism, I guess?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... File src/mainboard/foxconn/d41s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... PS1, Line 52: device pci 00.0 on end [out of topic] what is the difference between this and the one at line #30 please ?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... File src/mainboard/foxconn/d41s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... PS1, Line 52: device pci 00.0 on end
[out of topic] what is the difference between this and the one at line #30 please ?
It's in a different location / on a different bus. 1c.1 is the bridge, it will get a secondary bus number assigned, e.g. 2, so this devices would be 0000:02:00.0. While the one above will always be 0000:00:00.0.
Strictly speaking, the entry here is not necessary, btw. It's neither asso- ciated with a driver (chip) nor does it provide any information beyond the `on` which is the default. It results in a warning, though, if the device is failing.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... File src/mainboard/foxconn/d41s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... PS1, Line 52: device pci 00.0 on end
It's in a different location / on a different bus. 1c.1 is the bridge, it […]
Thank you.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38075
to look at the new patch set (#2).
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
mb/foxconn/d41s/devicetree.cb: Indent with tabs
As on most other boards, use tabs to indent the devicetree.
Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/foxconn/d41s/devicetree.cb 1 file changed, 89 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38075/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... File src/mainboard/foxconn/d41s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... PS1, Line 4: # Copyright (C) 2015 Damien Zammit damien@zamaudio.com : # Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz : # : # This program is free software; you can redistribute it and/or modify : # it under the terms of the GNU General Public License as published by : # the Free Software Foundation; either version 2 of the License, or : # (at your option) any later version. : # : # This program is distributed in the hope that it will be useful, : # but WITHOUT ANY WARRANTY; without even the implied warranty of : # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Too much automatism, I guess?
oops lol, fixed.
https://review.coreboot.org/c/coreboot/+/38075/1/src/mainboard/foxconn/d41s/... PS1, Line 52: device pci 00.0 on end
Thank you.
You can use `lspci -nntv` to make lspci print a tree diagram instead of a list
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38075 )
Change subject: mb/foxconn/d41s/devicetree.cb: Indent with tabs ......................................................................
mb/foxconn/d41s/devicetree.cb: Indent with tabs
As on most other boards, use tabs to indent the devicetree.
Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/foxconn/d41s/devicetree.cb 1 file changed, 89 insertions(+), 90 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 19d3e10..4ada05c 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -16,97 +16,96 @@ #
chip northbridge/intel/pineview # Northbridge - register "gfx.use_spread_spectrum_clock" = "0" - register "use_crt" = "1" - register "use_lvds" = "0" + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0"
- device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - subsystemid 0x105b 0x0d55 inherit - device pci 0.0 on end # Host Bridge - device pci 1.0 off end # PEG - device pci 2.0 on end # Integrated graphics controller - device pci 2.1 off end # Integrated graphics controller 2 - chip southbridge/intel/i82801gx # Southbridge - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x441" + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FCBGA559 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + subsystemid 0x105b 0x0d55 inherit + device pci 0.0 on end # Host Bridge + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 off end # Integrated graphics controller 2
- register "gen1_dec" = "0x00fc0a01" # Environment Controller + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x441"
- device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2 (NIC) - device pci 00.0 on end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1d.0 on end # USB - device pci 1d.1 on end # USB - device pci 1d.2 on end # USB - device pci 1d.3 on end # USB - device pci 1d.7 on end # USB - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio (not on nm10?) - #device pci 1e.3 off end # AC'97 Modem (not on nm10?) - device pci 1f.0 on # ISA bridge - chip superio/ite/it8721f # Super I/O - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # PP - io 0x60 = 0x378 - io 0x62 = 0 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0xa10 - io 0x62 = 0xa00 - irq 0x70 = 0 - end - device pnp 2e.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.a on # CIR - io 0x60 = 0x3e0 - irq 0x70 = 10 - end - end - end - device pci 1f.1 off end # PATA - device pci 1f.2 on end # SATA - device pci 1f.3 on # SMbus - chip drivers/i2c/ck505 - register "mask" = "{ 0x00, 0x80, 0xff, 0xff, - 0xff }" - register "regs" = "{ 0x00, 0x80, 0xfe, 0xff, - 0xfc }" - device i2c 69 on end - end - end - end - end + register "gen1_dec" = "0x00fc0a01" # Environment Controller + + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on end + end + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio (not on nm10?) + #device pci 1e.3 off end # AC'97 Modem (not on nm10?) + device pci 1f.0 on # ISA bridge + chip superio/ite/it8721f # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # PP + io 0x60 = 0x378 + io 0x62 = 0 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0 + end + device pnp 2e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a on # CIR + io 0x60 = 0x3e0 + irq 0x70 = 10 + end + end + end + device pci 1f.1 off end # PATA + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 + register "mask" = "{ 0x00, 0x80, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x00, 0x80, 0xfe, 0xff, 0xfc }" + device i2c 69 on end + end + end + end + end end
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Nico Huber (Code Review)