[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )

Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
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Patch Set 29:

(4 comments)

File src/soc/intel/pantherlake/gpio.c:

https://review.coreboot.org/c/coreboot/+/83789/comment/715a8f01_41b4bc4c?usp... :
PS17, Line 38: GPP_ASPIO
> agree. thx for the explanation! I will make the change.

I have changed GPP_ASPI0 to GPP_A in other places.

https://review.coreboot.org/c/coreboot/+/83789/comment/989c9a77_489e554f?usp... :
PS17, Line 54: 		.port = PID_GPIOCOM0,
> Hi Bubrata, It turns out that the port id is 16-bit in PTL. […]

sorry. my bad. typo Subrata:)

https://review.coreboot.org/c/coreboot/+/83789/comment/7d0aec0f_0417369b?usp... :
PS17, Line 112: GPP_CPUJTAG_H_ASPIO_VGPIO3
> > ASPI0 group is the GPP_A plus the SPI0 pads […]

Acknowledged

File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/83789/comment/757dd33c_a1f7e612?usp... :
PS28, Line 174: /* 48 */
> sure. I will remove these comments.

Acknowledged