Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29423 )
Change subject: soc/intel/braswell: Reserve IOAPIC and ROM resources ......................................................................
soc/intel/braswell: Reserve IOAPIC and ROM resources
The mmio resouces IOAPIC and ROM area not reserved. Reserve IOAPIC and ROM resources.
BUG=N/A TEST=Intel CherryHill CRB booting Embedded Linux
Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/braswell/southcluster.c 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index f389084..b8263db 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -20,6 +20,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <bootstate.h> #include "chip.h" #include <console/console.h> @@ -74,6 +75,10 @@ add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); + add_mmio_resource(dev, 0xfff, + 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB*KiB) + 1, + (CONFIG_COREBOOT_ROMSIZE_KB*KiB)); /* BIOS ROM */ + add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ }
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */