Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email )
Change subject: drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET ......................................................................
drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET
FSP reset status type is efi_return_status_t (not uint32_t) which size varies with the FSP binary architecture (32-bit vs 64-bit).
This commit defines FSP_STATUS_GLOBAL_RESET accordingly to PLATFORM_USES_FSP2_X86_32 and take care of the side effect of such 64-bit value.
BUG=b:348678529 TEST=Verified with fatcat mainboard on pantherlake reference board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/pantherlake/chip.c 5 files changed, 23 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84356/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8e9dcdc..40a4423 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -374,12 +374,18 @@ config FSP_STATUS_GLOBAL_RESET hex depends on SOC_INTEL_COMMON_FSP_RESET - default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 - default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 - default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 - default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 - default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 - default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 + default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 && PLATFORM_USES_FSP2_X86_32 + default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 + default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 + default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 + default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 default 0xffffffff help If global reset is supported by SoC then select the correct status value for global diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index 2626c39..983d4fc 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -41,7 +41,7 @@ die("unknown reset type"); }
-static uint32_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type) +static efi_return_status_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type) { efi_return_status_t status;
@@ -68,7 +68,7 @@ * If reset type is `EfiResetPlatformSpecific` then relying on pch_reset_data structure * to know if the reset type is a global reset. */ -uint32_t fsp_get_pch_reset_status(void) +efi_return_status_t fsp_get_pch_reset_status(void) { size_t size; const struct fsp_reset_hob *hob = fsp_find_extension_hob_by_guid(fsp_reset_guid, &size); diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index d9c6ac6..658223c 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -3,6 +3,8 @@ #ifndef _INTEL_COMMON_RESET_H_ #define _INTEL_COMMON_RESET_H_
+#include <efi/efi_datatype.h> + /* * Implement SoC specific global reset (i.e. a reset of both host and * ME partitions). Usually the ME is asked to perform the reset first. @@ -21,6 +23,6 @@ * If reset type if `EfiResetPlatformSpecific` then relying on pch_reset_data structure * to know if the reset type is a global reset. */ -uint32_t fsp_get_pch_reset_status(void); +efi_return_status_t fsp_get_pch_reset_status(void);
#endif /* _INTEL_COMMON_RESET_H_ */ diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 84b9235b2..326104d 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -264,7 +264,7 @@
static void soc_init_final_device(void *chip_info) { - uint32_t reset_status = fsp_get_pch_reset_status(); + efi_return_status_t reset_status = fsp_get_pch_reset_status();
if (reset_status == FSP_SUCCESS) return; @@ -273,8 +273,8 @@ fsp_handle_reset(reset_status);
/* Control shouldn't return here */ - die_with_post_code(POSTCODE_HW_INIT_FAILURE, - "Failed to handle the FSP reset request with error 0x%08x\n", reset_status); + fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE, + "Failed to handle the FSP reset request"); }
struct chip_operations soc_intel_meteorlake_ops = { diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 6b596b0..0d5406e 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -262,7 +262,7 @@
static void soc_init_final_device(void *chip_info) { - uint32_t reset_status = fsp_get_pch_reset_status(); + efi_return_status_t reset_status = fsp_get_pch_reset_status();
if (reset_status == FSP_SUCCESS) return; @@ -271,8 +271,8 @@ fsp_handle_reset(reset_status);
/* Control shouldn't return here */ - die_with_post_code(POSTCODE_HW_INIT_FAILURE, - "Failed to handle the FSP reset request with error 0x%08x\n", reset_status); + fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE, + "Failed to handle the FSP reset request"); }
struct chip_operations soc_intel_pantherlake_ops = {