[L] Change in coreboot[main]: mb/google/fatcat: Add GPIO settings

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Pranava Y N.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84405?usp=email )

Change subject: mb/google/fatcat: Add GPIO settings
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Patch Set 1:

(1 comment)

File src/mainboard/google/fatcat/variants/fatcat/gpio.c:

https://review.coreboot.org/c/coreboot/+/84405/comment/76fb35b2_4457490a?usp... :
PS1, Line 427: 	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
             : 	PAD_CFG_GPO(GPP_A08, 0, PLTRST),
             :
> Subrata, we don't use fw_config in early and romstage for our PTL and SoCs in the past. Jemery and I was trying to make the changes and we ran into several issues. There are some common code area that needs time to make it clean as well, as well Can we add a TODO list for using early stage fw_config and we can create a proper separate common code change and MB CLs later on?

I have two major questions about the GPIO configuration for fatcat.

1. Do we need all these different HW configurations? I assume the answer is TBD, and we will hear back from our HW team who took AI to get back on the fatcat SKU configuration. This will help us create fw_config.

2. Why do we need to program these GPIOs so early in the boot code, like PWR EN? If we need to meet the power seq diagram, then we need to bring FW config (varaint.c) in bootblock, which I would like to avoid as bootblock is part of RO code.