[M] Change in coreboot[main]: arch/riscv: Refactor SMP code

[Maximilian Brune (Code Review)]

Attention is currently required from: Philipp Hug, Ron Minnich.

Hello Philipp Hug, Ron Minnich, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81082?usp=email

to look at the new patch set (#5).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: arch/riscv: Refactor SMP code
......................................................................

arch/riscv: Refactor SMP code

Currently only a fixed number of harts/cores can be detected.

This patch adds a Kconfig option which allows to detect the number of
harts at runtime if a SOC or mainboard has a scheme to do so.
As part of that patch SMP logic has been mostly moved to smp_resume,
since it is easier to debug issues at the time smp_resume is called
than it is at smp_pause, since the serial is usually not present at the
time of the first smp_pause call.

Signed-off-by: Maximilian Brune 
Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587
---
M src/arch/riscv/Kconfig
M src/arch/riscv/include/arch/smp/smp.h
M src/arch/riscv/include/mcall.h
M src/arch/riscv/mcall.c
M src/arch/riscv/smp.c
5 files changed, 84 insertions(+), 49 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81082/5