[XS] Change in coreboot[main]: soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83729?usp=email )

Change subject: soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage
......................................................................

soc/intel/cannonlake/romstage: Initialize Intel TXT in romstage

Call intel_txt_romstage_init to let coreboot have control over as
much initialization as possible. The function will also call the
BIOS ACM SCLEAN if necessary.

TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled.

Change-Id: I5a667f2bb2d4fa658b4dafb556289021649dc0e0
Signed-off-by: Michał Żygowski 
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/83729/1

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index b3777b6..d586305 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -9,6 +9,7 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <memory_info.h>
+#include <security/intel/txt/txt.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -130,6 +131,10 @@
    cse_init(HECI1_BASE_ADDRESS);

s3wake = pmc_fill_power_state(ps) == ACPI_S3;
+
+	if (CONFIG(INTEL_TXT))
+		intel_txt_romstage_init();
+
    fsp_memory_init(s3wake);
    pmc_set_disb();
    if (!s3wake) {