[M] Change in coreboot[main]: soc/amd/common/acpi: Add SPI flash controller

[Felix Held (Code Review)]

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel.

Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84918?usp=email )

Change subject: soc/amd/common/acpi: Add SPI flash controller
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Patch Set 5:

(5 comments)

File src/soc/amd/common/acpi/spi.asl:

https://review.coreboot.org/c/coreboot/+/84918/comment/bbf184c4_76279e90?usp... :
PS5, Line 12:     
should be tabs for indentation

https://review.coreboot.org/c/coreboot/+/84918/comment/62282694_040fb5ab?usp... :
PS5, Line 33: 0xFEC10000
SPI_BASE_ADDRESS

https://review.coreboot.org/c/coreboot/+/84918/comment/84862fcc_6967c25a?usp... :
PS5, Line 46: store
please use asl2 syntax instead of the old asl1 syntax. usage of the asl1 syntax has been deprecated in coreboot and the asl2 syntax is easier to read

https://review.coreboot.org/c/coreboot/+/84918/comment/afac5f68_5ee3a086?usp... :
PS5, Line 55: RAR2
seems that that definition is missing; what is that supposed to do?

https://review.coreboot.org/c/coreboot/+/84918/comment/9c59166d_1e454263?usp... :
PS5, Line 57:             store (2, ASCE)
switching to use SPI_CS3_L when acquiring the spi controller semaphore and switching back to SPI_CS1_L when releasing it seems both questionable in general and board-specific to me