Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31446
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
mb/google/hatch: Select SD_PWR_EN workaround
Hatch implements acive high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31446/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 65a3562..a1e58a3 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_WHISKEYLAKE select SYSTEM_TYPE_LAPTOP
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31446 )
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31446 )
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31446/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31446/2//COMMIT_MSG@9 PS2, Line 9: acive active
Hello Patrick Rudolph, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31446
to look at the new patch set (#3).
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
mb/google/hatch: Select SD_PWR_EN workaround
Hatch implements acive high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31446/3
Hello Patrick Rudolph, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31446
to look at the new patch set (#4).
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
mb/google/hatch: Select SD_PWR_EN workaround
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31446/4
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31446 )
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31446/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31446/2//COMMIT_MSG@9 PS2, Line 9: acive
active
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31446 )
Change subject: mb/google/hatch: Select SD_PWR_EN workaround ......................................................................
Patch Set 5: Code-Review+2
Hello Patrick Rudolph, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31446
to look at the new patch set (#10).
Change subject: mb/google/hatch: Select SD_PWR_EN Active high config ......................................................................
mb/google/hatch: Select SD_PWR_EN Active high config
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31446/10
Hello Patrick Rudolph, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31446
to look at the new patch set (#15).
Change subject: mb/google/hatch: Select SD_PWR_EN Active high config ......................................................................
mb/google/hatch: Select SD_PWR_EN Active high config
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31446/15
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31446 )
Change subject: mb/google/hatch: Select SD_PWR_EN Active high config ......................................................................
Patch Set 15: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31446 )
Change subject: mb/google/hatch: Select SD_PWR_EN Active high config ......................................................................
mb/google/hatch: Select SD_PWR_EN Active high config
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-on: https://review.coreboot.org/c/31446 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b97977c..2290d8c 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_WHISKEYLAKE select SYSTEM_TYPE_LAPTOP