[S] Change in coreboot[master]: {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75767?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config
......................................................................

{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config

This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config
to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config
is clear.

Any platform would like to fetch the currently running ISH firmware
version should select this configuration.

TEST=Able to build and boot google/marasov.

Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767
Reviewed-by: Kangheui Won 
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
---
M src/drivers/intel/ish/ish.c
M src/mainboard/google/brya/Kconfig
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
6 files changed, 15 insertions(+), 14 deletions(-)

Approvals:
  Kangheui Won: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved

diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c
index 0415af0..a84be5b 100644
--- a/src/drivers/intel/ish/ish.c
+++ b/src/drivers/intel/ish/ish.c
@@ -63,7 +63,7 @@

static void intel_ish_final(struct device *dev)
 {
-	if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION))
+	if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION))
    	intel_ish_get_version();
 }

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b27945e..2a9941a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -87,7 +87,7 @@
    select SOC_INTEL_ALDERLAKE_PCH_N
    select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
    select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
-	select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION
+	select SOC_INTEL_STORE_ISH_FW_VERSION
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_TI50
    select SOC_INTEL_COMMON_MMC_OVERRIDE
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index f052279..7f24032 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -162,7 +162,7 @@
 }
 #endif

-#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)
+#if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
 /*
  * SoC override API to identify if ISH Firmware existed inside CSE FPT.
  *
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 26c623f..d809e03 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -45,22 +45,23 @@
      Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
      to make `HECI1` device disable using private configuration register (PCR) write.

-config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION
+config SOC_INTEL_STORE_ISH_FW_VERSION
    bool
    default n
    depends on DRIVERS_INTEL_ISH
    help
-	  This configuration option stores CSE FPT partitions' version in CBMEM memory.
-	  This information can be used to identify the currently running firmware partition
+	  This configuration option stores ISH version in CBMEM area.
+	  This information can be used to identify the currently running ISH firmware
      version.

-	  The cost of sending HECI command to read the CSE FPT is significant (~200ms)
-	  hence, the idea is to read the CSE RW version on every cold reset (to cover
-	  the CSE update scenarios) and store into CBMEM to avoid the cost of resending
-	  the HECI command in all consecutive warm boots.
+	  ISH BUP is sitting inside the CSE firmware partition. The way to retrieve the
+	  ISH version is by sending the HECI command to read the CSE FPT. The cost of sending
+	  HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to
+	  read the CSE RW version on every cold reset (to cover the CSE update scenarios)
+	  and store into CBMEM to avoid the cost of resending the HECI command in all
+	  consecutive warm boots.

-	  Later boot stages can just read the CBMEM ID to retrieve the ISH version if
-	  required.
+	  Later boot stages can just read the CBMEM ID to retrieve the ISH version.

Additionally, ensure this feature is platform specific hence, only enabled
      for the platform that would like to store the ISH version into the CBMEM and
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 733f68b..7063ecb 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1307,7 +1307,7 @@
     * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition
     * is available
     */
-	if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) &&
+	if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) &&
    		 soc_is_ish_partition_enabled()) {
    	store_cse_rw_fw_version();
    	store_ish_version();
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 23a4490..636b1f4 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -528,7 +528,7 @@
  * identifying the UFS enabled device is enough to conclude if ISH partition is
  * available.
  */
-#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)
+#if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
 bool soc_is_ish_partition_enabled(void);
 #else
 static inline bool soc_is_ish_partition_enabled(void)