[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Saurabh Mishra (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun, Wonkyu Kim.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 62:

(15 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/3d3c33c8_60c2df1d?usp... :
PS36, Line 53: 22
> Yes, it should be 4+8+4=16 for H SKU.

Acknowledged

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/cc9355c5_b66c6d7b?usp... :
PS48, Line 95: config P2SB_2_PCR_BASE_ADDRESS
> Can we use similar definition as PCR2_BASE_ADDRESS?

same comment for this. If Subrata agress, we can make the change.

File src/soc/intel/pantherlake/bootblock/pcd.c:

https://review.coreboot.org/c/coreboot/+/83354/comment/975361b7_d34e5f54?usp... :
PS47, Line 27: #define PCR_PSFX_TO_SHDW_BAR0	0
> Remove unused definitions […]

Acknowledged

https://review.coreboot.org/c/coreboot/+/83354/comment/2d8dbf3a_bc967dba?usp... :
PS47, Line 35: #define PCR_DMI_ACPIBA		0x27B4
> Remove unused definitions […]

Acknowledged

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/c79788f8_6b593246?usp... :
PS61, Line 23: #define EP_BASE_ADDRESS		0xfeda1000
> Can you check if this is sill used for PTL?

Hi Will, sure i will check and update.

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/8861bbed_bf8ce229?usp... :
PS48, Line 20: 2000000
> Can we use MiB instead of direct hex value?  And Can we also update all size value by using KiB and  […]

We can come back and make the changes in refactoring of bootblock. Currently this way writing is similar to  being used with n-1 platforms.

https://review.coreboot.org/c/coreboot/+/83354/comment/3a1c5e7c_31dd7daf?usp... :
PS48, Line 72: #define P2SB2_BAR		CONFIG_P2SB_2_PCR_BASE_ADDRESS
> Can we use like PCR2_BASE_ADDRESS?

This name was suggested by Subrata, we had resolved this query earlier to be using "P2SB_2_PCR_BASE_ADDRESS". Let me know what suites, will update accordingly.

File src/soc/intel/pantherlake/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/812d61c2_a2127197?usp... :
PS61, Line 75: #define  PCI_DEV_TCSS_XDCI	_PCI_DEV(TCSS, 1)
> Would you move this to the line between 78-79, after PCI_DEV_TCSS_XHCI?

Acknowledged

https://review.coreboot.org/c/coreboot/+/83354/comment/435cde09_696ca38b?usp... :
PS61, Line 97:
> remove the tab to align the indentation

Acknowledged

https://review.coreboot.org/c/coreboot/+/83354/comment/251b4911_090579d0?usp... :
PS61, Line 111: #define  PCI_DEV_IEH_0		_PCI_DEV(XHCI, 5)
              : #define  PCI_DEV_CNVI_BT	_PCI_DEV(XHCI, 7)
> move this after line 116-PCI_DEV_CNVI_WIFI?

Acknowledged

File src/soc/intel/pantherlake/include/soc/pcr_ids.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/024ceb3c_047b3b2d?usp... :
PS48, Line 14: #define PID_PSF15	0xB4
> For PID_PSFn, can you add only used define? […]

Yes, but as per Subrata, we have to push all the avaliable PIDs.

https://review.coreboot.org/c/coreboot/+/83354/comment/d1583c05_3f0a5cad?usp... :
PS48, Line 26: #define PID_DMI		0x2F
> This is dummy value.  Can you check if we remove this cause build error? […]

Sure, i will update this with my build recipe on fatcat MB.

https://review.coreboot.org/c/coreboot/+/83354/comment/57977e05_e6457e18?usp... :
PS48, Line 27: #define PID_NPK		0x8C
> PID_NPK is used?

Not used, removed.

https://review.coreboot.org/c/coreboot/+/83354/comment/f1c49962_81dfacb7?usp... :
PS48, Line 28: #define PID_XHCI	0x3A
> Is this value is correct? according to BIOS reference code USB Host controller P2SB id is 0x09.

Acknowledged

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/237711d8_adc441f0?usp... :
PS61, Line 80:
> suggesting to use tabs instead of spaces between GPE_STS_RSVD and GPE_STD

Acknowledged