Attention is currently required from: Angel Pons, Nicholas Chin.
Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email )
Change subject: mb/asrock: Add Z77 Extreme4 ......................................................................
Patch Set 10:
(12 comments)
File src/mainboard/asrock/z77_extreme4/Kconfig:
https://review.coreboot.org/c/coreboot/+/85772/comment/972ba1ea_a354bc99?usp... : PS10, Line 27: int
Type not needed here as it's defined in `sb/intel/bd82x6x/Kconfig`
Done
File src/mainboard/asrock/z77_extreme4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85772/comment/97297a51_a4f4ee11?usp... : PS10, Line 4: register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "4"
Move under igd device
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/7d628fab_a315e565?usp... : PS10, Line 24: register "gen1_dec" = "0x000c0291" : register "gen2_dec" = "0x000c0241" : register "gen3_dec" = "0x000c0251"
Move under lpc device (probably between subsystem and the superio)
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/0d01f1d2_d0d8a74a?usp... : PS10, Line 28: register "sata_interface_speed_support" = "0x3" : register "sata_port_map" = "0x3f"
Move under sata1 device
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/407095d4_01c93514?usp... : PS10, Line 32: register "superspeed_capable_ports" = "0x0000000f"
Move under xhci device
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/384559ad_a936d905?usp... : PS10, Line 49: register "xhci_overcurrent_mapping" = "0x00000c03" : register "xhci_switchable_ports" = "0x0000000f"
Move under xhci device
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/a765092c_e526de29?usp... : PS10, Line 57: device ref mei2 off end : device ref me_ide_r off end : device ref me_kt off end : device ref gbe off end
Defaults to off in chipset devicetree, could be removed
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/fbf21b94_774a8e25?usp... : PS10, Line 71: device ref pcie_rp2 off end : device ref pcie_rp3 off end
Defaults to off in chipset devicetree, could be removed
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/ecd48884_d65fbd29?usp... : PS10, Line 91: device ref pci_bridge off end
Defaults to off in chipset devicetree, could be removed.
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/67766911_fbe2e5fb?usp... : PS10, Line 157: end
Move to previous line
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/33d8cd55_b4d50923?usp... : PS10, Line 166: device ref sata2 off end : device ref thermal off end
Defaults to off in chipset devicetree, could be removed
Done
File src/mainboard/asrock/z77_extreme4/mainboard.c:
https://review.coreboot.org/c/coreboot/+/85772/comment/abf9e7d7_3b2c6d45?usp... : PS10, Line 5: #include <southbridge/intel/bd82x6x/pch.h>
Doesn't seem to be used, remove.
Done
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Riku Viitanen (Code Review)