Hello Aaron Durbin, Subrata Banik, Arthur Heymans, Michael Niewöhner, Duncan Laurie, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35984
to review the following change.
Change subject: soc/intel/pcie: Split up common PCIe RP device list ......................................................................
soc/intel/pcie: Split up common PCIe RP device list
Having a complete PCI device driver in common code is nice, as long as the whole driver is common. However, once any operation is chip specific, one wants to have control over the driver at chip level again.
The latter is the case now for `soc/intel/skylake` where we want to implement a less fragile detection for root-port swapping. So we keep the common functions common, and also provide default operation structs for the chips that don't need specific functions. When we'll add chip specific functions later, only that chip's code needs to be touched.
NB. Some common drivers already work around the issues of common operation structs by calling into chip code again from the common level (often with irritating weak functions). This cascading of abstraction mechanisms doesn't seem like a good option, it often leaves the overall code less readable (one has to look into chip code, then common code, then chip code again, ...) and less main- tainable.
Change-Id: I4f11073ed0a0fe07f5c5f5f5928200ad071731cf Signed-off-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/pcie.c A src/soc/intel/common/block/include/intelblocks/pcie.h M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/pcie.c M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/pcie.c 8 files changed, 248 insertions(+), 146 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35984/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 724e141..adee1ac 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c +ramstage-y += pcie.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/cannonlake/pcie.c b/src/soc/intel/cannonlake/pcie.c new file mode 100644 index 0000000..a1c3421 --- /dev/null +++ b/src/soc/intel/cannonlake/pcie.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pcie.h> + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &intel_default_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/pcie.h b/src/soc/intel/common/block/include/intelblocks/pcie.h new file mode 100644 index 0000000..a20e3dc --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pcie.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PCIE_H +#define SOC_INTEL_COMMON_BLOCK_PCIE_H + +/* + * These are default operations for Intel PCIe Root Ports. + * The structs below hook them up. However any SoC that needs + * a little more flexibility, can implement its own structs + * and use the functions directly. + */ + +void intel_pcie_init(struct device *dev); +void intel_pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset); + +extern struct pci_operations intel_default_pcie_pci_ops; +extern struct device_operations intel_default_pcie_ops; + +#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_H */ diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 9c95124..bd721a3 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -19,10 +19,11 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/pcie.h>
#define CACHE_LINE_SIZE 0x10
-static void pch_pcie_init(struct device *dev) +void intel_pcie_init(struct device *dev) { u16 reg16;
@@ -59,7 +60,7 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); }
-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) +void intel_pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) { /* Set max snoop and non-snoop latency for the SOC */ pci_write_config32(dev, offset, @@ -67,154 +68,16 @@ PCIE_LTR_MAX_SNOOP_LATENCY_3146US); }
-static struct pci_operations pcie_ops = { - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, +struct pci_operations intel_default_pcie_pci_ops = { + .set_L1_ss_latency = intel_pcie_set_L1_ss_max_latency, .set_subsystem = pci_dev_set_subsystem, };
-static struct device_operations device_ops = { +struct device_operations intel_default_pcie_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pch_pcie_init, + .enable_resources = pci_bus_enable_resources, + .init = intel_pcie_init, .scan_bus = pciexp_scan_bridge, - .ops_pci = &pcie_ops, -}; - -static const unsigned short pcie_device_ids[] = { - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, - 0 -}; - -static const struct pci_driver pch_pcie __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pcie_device_ids, + .ops_pci = &intel_default_pcie_pci_ops, }; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 15f7030..9dae6c4 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c +ramstage-y += pcie.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/icelake/pcie.c b/src/soc/intel/icelake/pcie.c new file mode 100644 index 0000000..587bc4a --- /dev/null +++ b/src/soc/intel/icelake/pcie.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pcie.h> + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &intel_default_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..b3919c6 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += me.c ramstage-y += memmap.c ramstage-y += p2sb.c +ramstage-y += pcie.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c new file mode 100644 index 0000000..815d166 --- /dev/null +++ b/src/soc/intel/skylake/pcie.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pcie.h> + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &intel_default_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +};
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35984 )
Change subject: soc/intel/pcie: Split up common PCIe RP device list ......................................................................
Patch Set 1:
Sorry for the noise, this doesn't seem needed atm.
Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35984 )
Change subject: soc/intel/pcie: Split up common PCIe RP device list ......................................................................
Abandoned
-
Nico Huber (Code Review)