Patch set updated for coreboot: 5b63293 Samus: Synchronization with FRC to enable PCIe Relaxed Order.

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9206

-gerrit

commit 5b632930942b2c44241954fb9f5f609a818582ed
Author: Kenji Chen 
Date:   Sat Sep 20 01:39:20 2014 +0800

Samus: Synchronization with FRC to enable PCIe Relaxed Order.

Signed-off-by: Stefan Reinauer 
    Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324
    Original-BUG=None
    Original-TEST=Modify settings, build and update the image to Samus and
    Original-check the settings are applied to Registers.
    Original-Signed-off-by: Kenji Chen 
    Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
    Original-Reviewed-on: https://chromium-review.googlesource.com/219073
    Original-Reviewed-by: Duncan Laurie

Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31
---
 src/soc/intel/broadwell/lpc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index d7a3e82..5efcb73 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -207,6 +207,9 @@ static const struct reg_script pch_misc_init_script[] = {
    /* Clear status bits to prevent unexpected wake */
    REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f),
    REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0),
+	/* Enable PCIe Releaxed Order */
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)),
+	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
    /* Setup SERIRQ, enable continuous mode */
    REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
 #if !CONFIG_SERIRQ_CONTINUOUS_MODE