Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss - coreboot-gerrit

20 Dec 2019


      Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 )
Change subject: soc/intel/tigerlake: Add code for early tcss
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Patch Set 1:
This change is ready for review.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e
Gerrit-Change-Number: 37870
Gerrit-PatchSet: 1
Gerrit-Owner: Shaunak Saha shaunak.saha@intel.com
Gerrit-Reviewer: Brandon Breitenstein brandon.breitenstein@intel.com
Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com
Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com
Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com
Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Fri, 20 Dec 2019 07:50:42 +0000
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