Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47538 )
Change subject: soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER ......................................................................
soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER
The PCH IOAPIC is not PCI discoverable. Linux checks the BDF set in DMAR against the PCI class if it is a PIC, which 00:1F.0 for instance isn't.
The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR 3, MINOR 7 if the BUS number is 0.
Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47538/1
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 33e257c..22ef4ab 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -111,7 +111,7 @@ #define HPET_DEV_NUM PCH_DEV_SLOT_LPC #define HPET0_FUNC_NUM 0x00
-#define PCH_IOAPIC_BUS_NUMBER 0x00 +#define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47538 )
Change subject: soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER ......................................................................
Patch Set 3: Code-Review+2
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47538 )
Change subject: soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER ......................................................................
soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER
The PCH IOAPIC is not PCI discoverable. Linux checks the BDF set in DMAR against the PCI class if it is a PIC, which 00:1F.0 for instance isn't.
The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR 3, MINOR 7 if the BUS number is 0.
Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/47538 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marc Jones marc@marcjonesconsulting.com --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 98c47fc..bcb2641 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -112,7 +112,7 @@ #define HPET_DEV_NUM PCH_DEV_SLOT_LPC #define HPET0_FUNC_NUM 0x00
-#define PCH_IOAPIC_BUS_NUMBER 0x00 +#define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00
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Arthur Heymans (Code Review) -
Marc Jones (Code Review)