[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.

Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )

Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
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Patch Set 117:

(3 comments)

File src/soc/intel/pantherlake/acpi/southbridge.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/aef2c5f2_51f40879?usp... :
PS104, Line 5: #include <soc/itss.h>
> Done

soc/itss.h removed.

File src/soc/intel/pantherlake/acpi/tcss_dma.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/11daf179_721df0b4?usp... :
PS104, Line 22: 	Offset (0xFF),
              : 	DMAD, 8         /* 31:24 DMA Active Delay */
> can you please point me at EDS chapter ?

I add TASK 17 for TODO item in https://partnerissuetracker.corp.google.com/issues/357011633 for Type-C DMA register description.

File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/68de35e0_6c7ac617?usp... :
PS104, Line 32: 	Offset (0x404),
              : 	LSOE,   1,
              : 	LNSE,   1,
> i don't see the register definition is part of EDS

checking with your