Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43881 )
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
mb/google/fizz: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I04e73bec38051b191bcb18ce179ff5d65e76655c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb 1 file changed, 119 insertions(+), 147 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43881/1
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d959b81..7976bed 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,27 +65,12 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -171,84 +156,6 @@ .dc_loadline = 310, }"
- # Enable Root port 3(x1) for LAN. - register "PcieRpEnable[2]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - # RP 3 uses SRCCLKREQ0# - register "PcieRpClkReqNumber[2]" = "0" - # RP 3, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" - # RP 3, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 - register "PcieRpClkSrcNumber[2]" = "0" - - # Enable Root port 4(x1) for WLAN. - register "PcieRpEnable[3]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[3]" = "1" - # RP 4 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[3]" = "5" - # RP 4, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[3]" = "1" - # RP 4, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 - register "PcieRpClkSrcNumber[3]" = "5" - - # Enable Root port 5(x4) for NVMe. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # RP 5 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[4]" = "1" - # RP 5, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # RP 5, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # RP 5 uses CLK SRC 1 - register "PcieRpClkSrcNumber[4]" = "1" - - # Enable Root port 9 for BtoB. - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[8]" = "2" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" - # RP 9, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[8]" = "2" - - # Enable Root port 11 for BtoB. - register "PcieRpEnable[10]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[10]" = "1" - # RP 11 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[10]" = "2" - # RP 11, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[10]" = "1" - # RP 11, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[10]" = "2" - - # Enable Root port 12 for BtoB. - register "PcieRpEnable[11]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[11]" = "1" - # RP 12 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[11]" = "2" - # RP 12, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[11]" = "1" - # RP 12, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[11]" = "2" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front @@ -256,7 +163,7 @@ register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C @@ -266,38 +173,8 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
- register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC - register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM - register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug - register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C5 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 194, - .scl_hcnt = 100, - .sda_hold = 36, - }, - }, }"
# Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -328,6 +205,10 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -383,53 +264,131 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.0 on # I2C #0: HDMI CEC + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + end + device pci 15.1 off # I2C #1: TPM + + # FIXME: This device is disabled, though? + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + end + device pci 15.2 on # I2C #2: Debug + register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" + end device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + }" + register "SataPortsDevSlp" = "{ \ + [0] = 0, \ + [1] = 1, \ + }" + end device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 19.1 on # I2C #5: Audio + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 194, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }" + end + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 - # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP - device pci 1c.2 on + device pci 1c.2 on # PCI Express Port 3: LAN (FSP swaps to port 1) + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "0" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpClkSrcNumber[2]" = "0" chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end register "device_index" = "0" end - end # PCI Express Port 3 - device pci 1c.3 on + end + device pci 1c.3 on # PCI Express Port 4 for WLAN + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "5" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "5" chip drivers/intel/wifi register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end - end # PCI Express Port 4 for WLAN - device pci 1c.4 on end # PCI Express Port 5 for NVMe + end + device pci 1c.4 on # PCI Express Port 5 for NVMe + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 for 2nd LAN + device pci 1d.0 on # PCI Express Port 9 for BtoB / 2nd LAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "2" chip drivers/net register "customized_leds" = "0x0fa5" register "device_index" = "1" device pci 00.0 on end end - end # PCI Express Port 9 for BtoB + end device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.2 on # PCI Express Port 11 for BtoB + register "PcieRpEnable[10]" = "1" + register "PcieRpClkReqSupport[10]" = "1" + register "PcieRpClkReqNumber[10]" = "2" + register "PcieRpAdvancedErrorReporting[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieRpClkSrcNumber[10]" = "2" + end + device pci 1d.3 on # PCI Express Port 12 for BtoB + register "PcieRpEnable[11]" = "1" + register "PcieRpClkReqSupport[11]" = "1" + register "PcieRpClkReqNumber[11]" = "2" + register "PcieRpAdvancedErrorReporting[11]" = "1" + register "PcieRpLtrEnable[11]" = "1" + register "PcieRpClkSrcNumber[11]" = "2" + end device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on + register "common_soc_config.gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" @@ -438,9 +397,14 @@ end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC + device pci 1e.4 off # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + end device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard + device pci 1e.6 on # SDCard + register "ScsSdCardEnabled" = "2" + end device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end @@ -448,9 +412,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43881
to look at the new patch set (#2).
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
mb/google/fizz: Relocate devicetree FSP settings
Also drop some redundant comments about these settings. Some settings do not seem to make sense, add FIXME comments to highlight that.
Tested with BUILD_TIMELESS=1, all three variants do not change.
Change-Id: I04e73bec38051b191bcb18ce179ff5d65e76655c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/fizz/variants/fizz/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb 4 files changed, 166 insertions(+), 208 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43881/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43881 )
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43881/2/src/mainboard/google/fizz/v... File src/mainboard/google/fizz/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43881/2/src/mainboard/google/fizz/v... PS2, Line 270: device pci 15.1 off end # I2C #1 1) So, this is off here in the devtree.
https://review.coreboot.org/c/coreboot/+/43881/2/src/mainboard/google/fizz/v... File src/mainboard/google/fizz/variants/endeavour/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43881/2/src/mainboard/google/fizz/v... PS2, Line 63: register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" 3) This setting was right here from the start. Why? What for?
https://review.coreboot.org/c/coreboot/+/43881/2/src/mainboard/google/fizz/v... PS2, Line 91: device pci 15.1 off # I2C #1: TPM 2) By inheritance, it is off here as well. Adding it doesn't change the binary.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43881
to look at the new patch set (#3).
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
mb/google/fizz: Relocate devicetree FSP settings
Also drop some redundant comments about these settings. Some settings do not seem to make sense, add FIXME comments to highlight that.
Tested with BUILD_TIMELESS=1, all three variants do not change.
Change-Id: I04e73bec38051b191bcb18ce179ff5d65e76655c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/fizz/variants/fizz/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb 4 files changed, 167 insertions(+), 209 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43881/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43881
to look at the new patch set (#4).
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
mb/google/fizz: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I04e73bec38051b191bcb18ce179ff5d65e76655c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb 1 file changed, 119 insertions(+), 147 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43881/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43881 )
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
Patch Set 4:
a
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43881 )
Change subject: mb/google/fizz: Relocate devicetree FSP settings ......................................................................
Patch Set 4: Code-Review+1
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43881
to look at the new patch set (#5).
Change subject: mb/google/fizz: Relocate devicetree settings ......................................................................
mb/google/fizz: Relocate devicetree settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I04e73bec38051b191bcb18ce179ff5d65e76655c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb 1 file changed, 119 insertions(+), 147 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43881/5
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43881 )
Change subject: mb/google/fizz: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)
-
Paul Menzel (Code Review)