Jenrus (Джэнрус) has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: ASUS P5Q support and menu entries added ......................................................................
ASUS P5Q support and menu entries added
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 3 files changed, 136 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/1
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index b59cd3c..e7d23bd 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -1,8 +1,9 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com # Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# Copyright (C) 2019 Ivan Vatlin jenrus@tuta.io # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ # GNU General Public License for more details. #
-if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO +if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -38,12 +39,14 @@ default "p5qc" if BOARD_ASUS_P5QC default "p5q_pro" if BOARD_ASUS_P5Q_PRO default "p5ql_pro" if BOARD_ASUS_P5QL_PRO + default "p5q" if BOARD_ASUS_P5Q
config MAINBOARD_PART_NUMBER string default "P5QC" if BOARD_ASUS_P5QC default "P5Q PRO" if BOARD_ASUS_P5Q_PRO default "P5QL PRO" if BOARD_ASUS_P5QL_PRO + default "P5Q" if BOARD_ASUS_P5Q
config DEVICETREE string diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name index 2a35036..22c0cca 100644 --- a/src/mainboard/asus/p5qc/Kconfig.name +++ b/src/mainboard/asus/p5qc/Kconfig.name @@ -6,3 +6,6 @@
config BOARD_ASUS_P5QL_PRO bool "P5QL PRO" + +config BOARD_ASUS_P5Q + bool "P5Q" diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb new file mode 100644 index 0000000..d17a94e --- /dev/null +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -0,0 +1,128 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# Copyright (C) 2019 Ivan Vatlin jenrus@tuta.io +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 on end # PEG + device pci 2.0 off end # Integrated graphics controller + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + + device pci 19.0 off end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 slot 1 + device pci 1c.1 on end # PCIe 2 slot 2 + device pci 1c.2 on end # PCIe 3 slot 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 on end # PCIe 5 MARVELL IDE + device pci 1c.5 on end # PCIe 6 ethernet NIC + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83667hg-a # Super I/O + device pnp 2e.0 off end # FDC + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + # Global registers + irq 0x2a = 0x00 + irq 0x2c = 0x22 + irq 0x2d = 0x00 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off end # SPI1 + device pnp 2e.107 off end # GPIO6 + device pnp 2e.207 off end # GPIO7 + device pnp 2e.307 on # GPIO8 + irq 0xe4 = 0xfb + irq 0xe5 = 0x02 + end + device pnp 2e.407 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xfe = 0x07 + end + device pnp 2e.309 on end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # 3VSBSW# enable + irq 0xe5 = 0x02 + irq 0xf2 = 0xfc + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 0 + # IRQ purposefully not assigned to prevent lockups + end + device pnp 2e.c on end # PECI + device pnp 2e.d on end # VID_BUSSEL + device pnp 2e.f on end # GPIO_PP_OD + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end # IDE + device pci 1f.6 off end + end + end +end
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: ASUS P5Q support and menu entries added ......................................................................
Patch Set 1:
(5 comments)
Hi, welcome to coreboot!
I've got a few suggestions for you. If you have any questions, feel free to ask me anything :-)
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1: Does this work? I would recommend listing in the commit message:
- What is tested and works - What does not work - What is untested
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@7 PS1, Line 7: ASUS P5Q support and menu entries added Commit messages should use imperative tense, as well as the scope of the change as a prefix. For example:
mb/asus/p5qc: Add ASUS P5Q as a variant
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@10 PS1, Line 10: There's no `Signed-off` line, which is probably why Jenkins marked the change as failed.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 55: config GPIO_C The GPIO settings might be different for the Asus P5Q. I would suggest using util/inteltool to dump the GPIO registers, running the stock Asus BIOS. The meaning of the registers can be found in the ICH10 datasheet.
You can also use this to generate a gpio.c:
https://github.com/Th3Fanbus/gpio-scripts/blob/master/gengpio.c
I know, it's an ugly hack of a program. To use it, you need to paste the values from inteltool into the corresponding variables:
GPIO_USE_SEL GP_IO_SEL GP_LVL GPI_INV GPIO_USE_SEL2 GP_IO_SEL2 GP_LVL2
Note that there's an additional GPIO bank. This only exists on Sandybridge and newer, so you should trim the resulting gpio.c
In any case, if you show me the register values with the stock Asus BIOS, I can check if the GPIO configuration is correct.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
PS1: This looks very similar to the existing devicetrees. Has anything been changed?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: ASUS P5Q support and menu entries added ......................................................................
Patch Set 1:
(1 comment)
Ivan, welcome to coreboot!
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
Does this work? I would recommend listing in the commit message: […]
… and document that *also* in `Documentation/`.
Jenrus (Джэнрус) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: ASUS P5Q support and menu entries added ......................................................................
Patch Set 1:
(4 comments)
Patch Set 1:
(5 comments)
Hi, welcome to coreboot!
I've got a few suggestions for you. If you have any questions, feel free to ask me anything :-)
TL:DR; Looks like I need to fix these errors & commit it again ¯_(ツ)_/¯ (excuse me if any kind of emoji is prohibited here)
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
… and document that *also* in `Documentation/`.
Hi, thanks for constructive criticism! As much as I use it, the only things tested so far are: -RAM (I using all 4 slots and I have all my 8Gb) -SATA (My two HDDs works fine) -Peripherals (There is no integrated graphics so I use 750Ti) -Audio (at least headphones output and mic input) -USB (My mouse, pen drives & Wi-Fi adapter works) -PS/2 (My good old keyboard works too) What is not tested: -S/PDIF & CD audio in -LAN -IEEE1394 (aka FireWire) -IDE & Floppy -TPM (AFAIK it's not working for sure)
About writing docs, could anyone link me some well-written one as a reference?
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@7 PS1, Line 7: ASUS P5Q support and menu entries added
Commit messages should use imperative tense, as well as the scope of the change as a prefix. […]
Guess I need to recommit my "work" :)
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@10 PS1, Line 10:
There's no `Signed-off` line, which is probably why Jenkins marked the change as failed.
I haven't any exp w/ with Gerrit & Jenkins, so I guess it's only my fault
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
PS1:
This looks very similar to the existing devicetrees. […]
I copypasted the device tree from "p5qc/" variant for any possible future work but guess they right about good intetions & hell
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#2).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 3 files changed, 136 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/2
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#3).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name 2 files changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/3
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
Patch Set 3:
(4 comments)
I really can't compare it for now, so here is dump from inteltool: https://pastebin.com/dB1RQa2B Also marked "done" all solved (IMHO) problems
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@7 PS1, Line 7: ASUS P5Q support and menu entries added
Guess I need to recommit my "work" :)
Done
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@10 PS1, Line 10:
I haven't any exp w/ with Gerrit & Jenkins, so I guess it's only my fault
Done
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 55: config GPIO_C
The GPIO settings might be different for the Asus P5Q. […]
Here is GPIO registers: https://pastebin.com/dB1RQa2B
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
PS1:
I copypasted the device tree from "p5qc/" variant for any possible future work but guess they right […]
Done
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
Patch Set 3:
(1 comment)
How can i send board_status about P5Q, not P5QC. Is it because of P5Q is a variant of P5QC in repo?
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
Hi, thanks for constructive criticism! […]
About working state on P5Q: yes, it works, I also sent board_status but it marked as P5QC. What a shame
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#4).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off by: Ivan Vatlin jenrus@tuta.io --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name 2 files changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
Patch Set 4:
(19 comments)
Patch Set 1:
(4 comments)
Patch Set 1:
(5 comments)
Hi, welcome to coreboot!
I've got a few suggestions for you. If you have any questions, feel free to ask me anything :-)
TL:DR; Looks like I need to fix these errors & commit it again ¯_(ツ)_/¯ (excuse me if any kind of emoji is prohibited here)
Oh, using emojis is perfectly fine. What's more, have you seen our 404 error page? https://review.coreboot.org/c/nothing
Patch Set 3:
I really can't compare it for now, so here is dump from inteltool: https://pastebin.com/dB1RQa2B Also marked "done" all solved (IMHO) problems
Perfect, thank you. Did you make this log while running coreboot, or with the stock BIOS? I would need a log with the stock BIOS.
Patch Set 3:
How can i send board_status about P5Q, not P5QC. Is it because of P5Q is a variant of P5QC in repo?
Yes, board_status doesn't know about variants yet. Even then, it has been very useful to double-check some things.
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
About working state on P5Q: yes, it works, I also sent board_status but it marked as P5QC. […]
Congrats on your first working coreboot port :)
Right, board_status doesn't know about variants yet. Still, thanks for uploading a report, the coreboot log is quite useful :)
For documentation, I think you can use this as a reference:
https://doc.coreboot.org/mainboard/intel/dg43gt.html
You can find the .md source file in the `Documentation` subfolder in the coreboot repo.
That Intel board does not work with in-circuit flashing, which consists of using an external programmer while the flash chip is still connected to the mainboard. It likely does not work on the Asus P5Q either, but since it has a socketed flash chip, you don't need to flash in-circuit: just remove the flash chip carefully. So, that part should be changed for the Asus P5Q documentation.
About untested things, here's some suggestions for testing various things. I've also included basic checks for things that need extra hardware: that way, even if not tested fully, they are likely to work well :D
- Does the RS232 port work? If it does, coreboot can output its logs through it, which is very useful when debugging things.
- If you have some conventional PCI cards, it would be nice to test the PCI slots. Pro-tip: use an Ethernet card with a boot ROM on it. Since it appears as a boot option on SeaBIOS, you don't need to boot to the OS, so it is faster :^) To do this, I have some 3Com cards which look like this one, but have a chip in the PLCC socket (top right corner):
https://i.ebayimg.com/images/g/JyQAAOSwxa9avWvz/s-l1600.jpg
- Please confirm that ACPI S3 (suspend to RAM) works. That is, that the mainboard can go to sleep and resume successfully. If it works fine, I would also run a longer test: for example, put it to sleep before going to bed, and check if it resumes fine the next morning.
- LAN probably works, looks like kinux can load the driver correctly, so if a MAC address is present it should work fine. Test if the MAC address stays after unplugging the mainboard, just in case the NIC keeps the MAC address set by the vendor firmware.
- Floppy might not work, but who needs it anyway? In any case, I could check if it works on the P5QL PRO, as these mainboards are quite similar.
- The TPM slot needs additional code. If you don't have a TPM installed, I would not bother. If somebody wants to use it, support can be added rather easily.
- The FireWire controller shows up in lspci and its driver loads fine, so it should work.
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@7 PS1, Line 7: ASUS P5Q support and menu entries added
Done
Yes, you can use `git commit --amend`. As long as the Change-Id line remains unchanged, Gerrit will treat the new commit as a new patchset of this change.
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@10 PS1, Line 10:
Done
Everybody forgets to sign-off from time to time :P
If you have configured git properly, you can use `git commit -s` for new commits, which adds the sign-off automatically.
https://review.coreboot.org/c/coreboot/+/38143/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38143/4//COMMIT_MSG@10 PS4, Line 10: Signed-off by Missing a `-`: Signed-off-by
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 55: config GPIO_C
Here is GPIO registers: https://pastebin. […]
I've checked and it matches the current gpio.c file. Did you make this log with the stock BIOS or with coreboot?
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 64: # The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable : # bogus disk. Compiling SeaBIOS without ATA support is a workaround. : : # The Asus P5QL PRO's Marvell controller (88SE6102-NNC2) does not need this, apparently. Does the Asus P5Q have a Marvell 88SE6102? lspci seems to differ, but the best way to know is to look at the physical chip on the board.
https://review.coreboot.org/c/coreboot/+/38143/4/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/4/src/mainboard/asus/p5qc/Kco... PS4, Line 39: default "p5qc" if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q I've added some suggestions to the devicetree on Patchset 1, so you might have to undo this.
I can see why you would want to do this, though: the boards are very similar, so having a full devicetree is inefficient. The best solution would be another commit to make these boards use overridetrees, but this can be done later.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
PS1:
Done
Right. Some things are different on the Asus P5Q, so I will open comments on them.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 29: end Personally, I like to align these `end` keywords. If you want, you can do it as well, but it's not a requirement. I think I might have OCD :P
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 30: device pci 1.0 on end # PEG Note: This port on the northbridge is where the GPU is connected.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 31: device pci 2.0 off end # Integrated graphics controller : device pci 2.1 off end # Integrated graphics controller 2 These devices don't exist on the P45 northbridge, so you can remove these lines
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 33: device pci 3.0 off end # ME : device pci 3.1 off end # ME : device pci 3.2 off end # ME : device pci 3.3 off end # ME Since these Asus boards don't have any ME firmware, the ME devices should be disabled by default, so these lines can be removed.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 41: # Set AHCI mode. This comment is outdated (AHCI mode was made the default option, because it's better).
You can instead describe what the value in the `sata_port_map` register does. In short, it's a bitfield that indicates which of the six SATA ports on the ICH10 southbridge should be enabled. On this board, all of them should be enabled. So the comment can be changed to:
# Enable all six SATA ports.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 43: register "sata_clock_request" = "0" : register "sata_traffic_monitor" = "0" You can remove these entries. The default value is zero already.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 58: device pci 1c.0 on end # PCIe 1 slot 1 The used PCIe ports may be different on the P5Q. You can check `lspci` while running the stock BIOS. Specifically, `lspci -nntv` shows which device is connected to which PCIe root port (the `1c.x` devices). With these logs, we can compare and see if anything is wrong.
I have used this picture as a reference. Am I looking at the correct board?
http://diy.yesky.com/imagelist/2008/167/1b529813etl1.jpg
From the kernel log of your board_status:
- 1c.0 has a [1106:3483] VIA Labs VL805 USB 3.0 Host Controller. - 1c.1 is empty. - 1c.2 has a [11ab:6121] Marvell 88SE6121 SATA II Controller. - 1c.3 is disabled. - 1c.4 has a [1969:1026] Atheros AR8121/AR8113/AR8114 PCI-E Ethernet Controller. - 1c.5 has a [11c1:5811] LSI FW322/323 [TrueFire] 1394a Controller.
Let me guess... the USB 3.0 controller is on a PCIe expansion card. The other devices would be part of the mainboard.
You can test the other PCIe slot with the USB 3.0 card. If the GPU is so bulky it blocks other slots, you can still grab a coreboot log through the RS232 port without a graphics card. Of course, you would need another computer with a serial port (or an USB-to-RS232 adapter).
What seems to be missing is the Silicon Image SATA II controller. Instead, there's a Marvell SATA II controller. Maybe I am not looking at the correct mainboard? It could also be that the Silicon Image controller is connected to the disabled `1c.3` PCIe port. Logs will help.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 70: chip superio/winbond/w83667hg-a You can use `util/superiotool` while running the stock BIOS to double-check these registers. Note that offset 0x30 indicates whether a certain device is enabled or not.
The SuperIO datasheet isn't avaliable on the internet, but you can request it from Nuvoton. (that's how I obtained it)
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 106: irq 0xe4 = 0x10 # 3VSBSW# enable Even if superiotool does not set bit 4 of this register, it should be enabled. Otherwise, the RAM loses power when the board goes to sleep (suspend to RAM), and then resume does not work.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 120: device pci 1f.1 off end # PATA/IDE This device does not exist on ICH10, so you can remove this line
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 124: IDE Strictly speaking, this is still SATA, but when it's configured in Legacy mode.
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name 2 files changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/5
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I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 3 files changed, 127 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/6
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
Patch Set 6:
(16 comments)
I added back devicetree.cb for P5Q
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
Congrats on your first working coreboot port :) […]
Okay, I'll try write something useful in doc :)
- My RS232-USB cable and gender changer for it are still delivering to me (I hate international delivery), so ASAP I will try&test it - PCI card? I don't have one but I guess I can buy it to test slots - Okay, I'll test it - As soon as I find my old router, I could test this too - Hey, there is no reason to drop floppy support (I'll try to buy it too) - I can't test TPM since it's optional plugable module - Test FireWire: check
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG@10 PS1, Line 10:
Everybody forgets to sign-off from time to time :P […]
How could I add automatically Signed-off-by? Sorry, some sort of git noob
https://review.coreboot.org/c/coreboot/+/38143/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38143/4//COMMIT_MSG@10 PS4, Line 10: Signed-off by
Missing a `-`: […]
Yikes!
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 55: config GPIO_C
I've checked and it matches the current gpio.c file. […]
I did it on stock BIOS as you wrote I am the kind of person who reads several times to be sure (even contracts)
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 64: # The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable : # bogus disk. Compiling SeaBIOS without ATA support is a workaround. : : # The Asus P5QL PRO's Marvell controller (88SE6102-NNC2) does not need this, apparently.
Does the Asus P5Q have a Marvell 88SE6102? lspci seems to differ, but the best way to know is to loo […]
My lspci output is: [jenrus@bbox inteltool]$ lspci | grep Marvell 03:00.0 IDE interface: Marvell Technology Group Ltd. 88SE6111/6121 SATA II / PATA Controller (rev b2)
https://review.coreboot.org/c/coreboot/+/38143/4/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/4/src/mainboard/asus/p5qc/Kco... PS4, Line 39: default "p5qc" if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q
I've added some suggestions to the devicetree on Patchset 1, so you might have to undo this. […]
I'll think about it, sounds like lotta work
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 29: end
Personally, I like to align these `end` keywords. […]
Aligned
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 31: device pci 2.0 off end # Integrated graphics controller : device pci 2.1 off end # Integrated graphics controller 2
These devices don't exist on the P45 northbridge, so you can remove these lines
Deleted
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 33: device pci 3.0 off end # ME : device pci 3.1 off end # ME : device pci 3.2 off end # ME : device pci 3.3 off end # ME
Since these Asus boards don't have any ME firmware, the ME devices should be disabled by default, so […]
Deleted
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 41: # Set AHCI mode.
This comment is outdated (AHCI mode was made the default option, because it's better). […]
Changed
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 43: register "sata_clock_request" = "0" : register "sata_traffic_monitor" = "0"
You can remove these entries. The default value is zero already.
Deleted
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 58: device pci 1c.0 on end # PCIe 1 slot 1
The used PCIe ports may be different on the P5Q. You can check `lspci` while running the stock BIOS. […]
Okay, I'll try to enable Silicon Image controller
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 70: chip superio/winbond/w83667hg-a
You can use `util/superiotool` while running the stock BIOS to double-check these registers. […]
Okay, I'll check it
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 106: irq 0xe4 = 0x10 # 3VSBSW# enable
Even if superiotool does not set bit 4 of this register, it should be enabled. […]
Should I change somrthing here?
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 120: device pci 1f.1 off end # PATA/IDE
This device does not exist on ICH10, so you can remove this line
Deleted
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 124: IDE
Strictly speaking, this is still SATA, but when it's configured in Legacy mode.
So what should I do with it?
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 3 files changed, 127 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/7
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 3 files changed, 127 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/8
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I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 190 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/9
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 190 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/10
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 10:
(1 comment)
Well, I added some sort of documentation
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 58: device pci 1c.0 on end # PCIe 1 slot 1
Okay, I'll try to enable Silicon Image controller
Just reflashed w/ Silicon Image SIL3114 support and enabled 1c.3 port Here's log: [jenrus@bbox ~]$ lspci | grep 1c.3 00:1c.3 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 4
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I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 190 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/11
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 11:
(1 comment)
I dumped SuperIO info
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 70: chip superio/winbond/w83667hg-a
Okay, I'll check it
Here's my superiotool log on stock BIOS: [jenrus@bbox superiotool]$ sudo ./superiotool superiotool r4.11-617-g22ba862717 Found Winbond W83667HG (id=0xa5, rev=0x13) at 0x2e
I'll need to edit doc to delete chip suffix since it's not important
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 11:
(1 comment)
Here is superiotool dump on stovk BIOS: https://pastebin.com/jqf8vxEG
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 70: chip superio/winbond/w83667hg-a
Here's my superiotool log on stock BIOS: […]
I understood how should I dump registers so here it is: https://pastebin.com/jqf8vxEG
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
Okay, I'll try write something useful in doc :) […]
Just tested sleep mode (not hibernate, i don't have swap to do it) and it works, so ACPI S3 -- check out
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38143/11/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/11/Documentation/mainboard/as... PS11, Line 28: : ### Internal programming : : The SPI flash can be accessed internally using [flashrom]. : : ```bash : $ flashrom -p internal -w coreboot.rom : ``` : : ### External programming : The SPI flash can be accessed externally using `CH341A` : : ```bash : $ flashrom -p ch341a_spi -w coreboot.rom : ``` please link to existing guides in Documentation/flash_tutorial.
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 187 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/12
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 12:
(1 comment)
Some documentation editing (w/ listing untested & not working features, comment if I forgot something)
https://review.coreboot.org/c/coreboot/+/38143/11/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/11/Documentation/mainboard/as... PS11, Line 28: : ### Internal programming : : The SPI flash can be accessed internally using [flashrom]. : : ```bash : $ flashrom -p internal -w coreboot.rom : ``` : : ### External programming : The SPI flash can be accessed externally using `CH341A` : : ```bash : $ flashrom -p ch341a_spi -w coreboot.rom : ```
please link to existing guides in Documentation/flash_tutorial.
Hi, Arthur! Thanks for your comment, I replaced all my flashing guides with link suggested by you. Do you have any other remarks?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 12: Code-Review+1
(15 comments)
It's pretty good, some minor things and it should be good to go
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
Just tested sleep mode (not hibernate, i don't have swap to do it) and it works, so ACPI S3 -- check […]
Right, so the tested and working things can go into the documentation. Things like FireWire should be marked as "Untested", but specifying that it is likely to work:
- FireWire: PCI device shows up and driver loads, no further test.
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 3: desktop desktop *board*
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 9: The following things are untested on this coreboot port: Add an extra blank line before untested things
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 27: No? Untested, likely does not work.
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 29: SOIC-8 Socketed DIP-8
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 53: Intel ME? It is disabled (does not have any firmware) on your board
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 55: ??? See mainboard: http://diy.yesky.com/imagelist/2008/167/1b529813etl1.jpg
Notice the square chip left of the blue PCIe x16 slot, south of the first PCIe x1 slot (PCIEX1_1). That is the clock generator.
And it is a *squints eyes* `ICS 9LPRS918JKLF` ?
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... File src/mainboard/asus/p5qc/Kconfig:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 55: config GPIO_C
I did it on stock BIOS as you wrote […]
Then it's a perfect match, so all good :D
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/Kco... PS1, Line 64: # The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable : # bogus disk. Compiling SeaBIOS without ATA support is a workaround. : : # The Asus P5QL PRO's Marvell controller (88SE6102-NNC2) does not need this, apparently.
My lspci output is: […]
Right, that seems to be the buggy controller type, so this section doesn't need changes.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 58: device pci 1c.0 on end # PCIe 1 slot 1
Just reflashed w/ Silicon Image SIL3114 support and enabled 1c.3 port […]
That doesn't show what is connected to the 1c.3 port. Do you have the full lspci log?
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 70: chip superio/winbond/w83667hg-a
I understood how should I dump registers so here it is: https://pastebin. […]
Thanks, only saw one thing (floppy should be enabled, see below)
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 71: device pnp 2e.0 off end # FDC : device pnp 2e.1 off end # LPT1 : device pnp 2e.2 on # COM1 : # Global registers : irq 0x2a = 0x00 : irq 0x2c = 0x22 : irq 0x2d = 0x00 : io 0x60 = 0x3f8 : irq 0x70 = 4 : end Floppy is enabled on your board:
device pnp 2e.0 on # FDC # Global registers irq 0x2a = 0x00 irq 0x2c = 0x22 irq 0x2d = 0x00 # Floppy io 0x60 = 0x3f0 irq 0xf0 = 0x0e end device pnp 2e.1 off end # LPT1 device pnp 2e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 93: 0x02 Your board has 0x82, but it's probably because some GPIOs are used as inputs. If things work fine, I'd leave it as-is.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 106: irq 0xe4 = 0x10 # 3VSBSW# enable
Should I change somrthing here?
Nope, all good.
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 124: IDE
So what should I do with it?
If you want, you can update the comment. It's not critical, though
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 201 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/13
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 13:
(9 comments)
I'll post `lspci -nntv` log later
https://review.coreboot.org/c/coreboot/+/38143/1//COMMIT_MSG Commit Message:
PS1:
Right, so the tested and working things can go into the documentation. […]
With so much items in list I should use a three column table (IMHO)
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 3: desktop
desktop *board*
Fixed
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 9: The following things are untested on this coreboot port:
Add an extra blank line before untested things
Still mastering my markdown, fixed
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 27: No?
Untested, likely does not work.
Deleted since chip is socketed
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 29: SOIC-8
Socketed DIP-8
Changed
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 53: Intel ME?
It is disabled (does not have any firmware) on your board
Changed
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 55: ???
See mainboard: http://diy.yesky.com/imagelist/2008/167/1b529813etl1.jpg […]
Thanks for your sharp eyes :D
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 71: device pnp 2e.0 off end # FDC : device pnp 2e.1 off end # LPT1 : device pnp 2e.2 on # COM1 : # Global registers : irq 0x2a = 0x00 : irq 0x2c = 0x22 : irq 0x2d = 0x00 : io 0x60 = 0x3f8 : irq 0x70 = 4 : end
Floppy is enabled on your board: […]
I connected my old FDD to test it but OS didn't detect floppy disk Need some workaround
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 124: IDE
If you want, you can update the comment. […]
Changed
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 13:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/12/Documentation/mainboard/as... PS12, Line 27: No?
Deleted since chip is socketed
Ack
https://review.coreboot.org/c/coreboot/+/38143/13/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/13/Documentation/mainboard/as... PS13, Line 8: Add:
+ All 4 DIMM slots + S3 suspend and resume + Red SATA ports
https://review.coreboot.org/c/coreboot/+/38143/13/Documentation/mainboard/as... PS13, Line 19: ATA PATA
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 71: device pnp 2e.0 off end # FDC : device pnp 2e.1 off end # LPT1 : device pnp 2e.2 on # COM1 : # Global registers : irq 0x2a = 0x00 : irq 0x2c = 0x22 : irq 0x2d = 0x00 : io 0x60 = 0x3f8 : irq 0x70 = 4 : end
I connected my old FDD to test it but OS didn't detect floppy disk […]
Floppy is still off on the last patchset, no wonder why it doesn't work :D
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#14).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 209 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/14
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#15).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 212 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/15
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#16).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 212 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/16
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 16:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38143/13/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/13/Documentation/mainboard/as... PS13, Line 8:
Add: […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/13/Documentation/mainboard/as... PS13, Line 19: ATA
PATA
Ack
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 58: device pci 1c.0 on end # PCIe 1 slot 1
That doesn't show what is connected to the 1c.3 port. […]
Here it is: https://pastebin.com/40cqNrDV
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 71: device pnp 2e.0 off end # FDC : device pnp 2e.1 off end # LPT1 : device pnp 2e.2 on # COM1 : # Global registers : irq 0x2a = 0x00 : irq 0x2c = 0x22 : irq 0x2d = 0x00 : io 0x60 = 0x3f8 : irq 0x70 = 4 : end
Floppy is still off on the last patchset, no wonder why it doesn't work :D
Tested it w/ your patch, didnt work either
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#17).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 208 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/17
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#18).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 208 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/18
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 18: Code-Review+2
(10 comments)
Silicon Image mystery is solved :)
Only thing to do is update the PCIe port description and change a few minor things.
https://review.coreboot.org/c/coreboot/+/38143/18/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/18/Documentation/mainboard/as... PS18, Line 66: model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) Nit: use capitals for names
Model f4x, f6x, 1067x (Pentium 4, D, Core 2)
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 58: device pci 1c.0 on end # PCIe 1 slot 1
Here it is: https://pastebin. […]
I've checked the boardview, and everything makes sense now.
PCIe devices: - Device 1c.0 --> PCIEX1_1 slot - Device 1c.1 --> PCIEX1_2 slot - Device 1c.2 --> (empty) - Device 1c.3 --> (empty) - Device 1c.4 --> Marvell 88SE6121 SATA/IDE controller - Device 1c.5 --> Atheros AR8121 Ethernet NIC
PCI devices: - Device 1e.0 --> 3x PCI slots and LSI FW322 FireWire controller
Aaand the Silicon Image SIL5723 is connected to... Marvell 88SE6121 SATA port 0?
I investigated a bit, and it makes sense now.
The Marvell chip is a PCIe to ATA controller. There are two pin-compatible versions: - 88SE6111: PCIe x1 to 1x IDE and 1x SATA, no RAID - 88SE6111: PCIe x1 to 1x IDE and 2x SATA, supports RAID 0 or 1 on SATA
Note that the Marvell RAID is not "true" RAID, it relies on driver software to do RAID. I guess the Asus mainboard designers wanted real RAID, so they just threw in a SIL5723. The Silicon Image SIL5723 is a port multiplier with hardware support for RAID. It is configured using physical strap pins, and one of the modes allows software control.
On the Asus P5Q, SATA is wired as follows: - The six red SATA ports are directly connected to the ICH10's six SATA ports. - The orange and white SATA ports go to the SIL5723 ports 0 and 1, respectively. - The SIL5723 is connected to the 88SE6121 port 0. - The 88SE6121 port 1 is unconnected.
On the Asus P5Q, the SIL5723 straps are directly wired to ICH10 GPIO pins: - GPIO57 --> CFG0 - GPIO39 --> CFG1 - GPIO23 --> CFG2 - GPIO28 --> RAID mode trigger
Strapping table: https://cdn.mos.cms.futurecdn.net/2GpyCMvfJzbYYsYFarfJ2W-650-80.png Source: https://www.tomshardware.com/reviews/silicon-image-brings-virtualization-esa...
https://review.coreboot.org/c/coreboot/+/38143/1/src/mainboard/asus/p5qc/var... PS1, Line 71: device pnp 2e.0 off end # FDC : device pnp 2e.1 off end # LPT1 : device pnp 2e.2 on # COM1 : # Global registers : irq 0x2a = 0x00 : irq 0x2c = 0x22 : irq 0x2d = 0x00 : io 0x60 = 0x3f8 : irq 0x70 = 4 : end
Tested it w/ your patch, didnt work either
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 50: PCIe 1 slot 1 State: on
Comment: PCIe 1: PCIEX1_1 slot
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 51: PCIe 2 slot 2 State: on
Comment: PCIe 2: PCIEX1_2 slot
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 52: PCIe 3 slot 3 State: off
Comment: PCIe 3: Unconnected
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 53: PCIe 4 (Silicon Image?) State: off
Comment: PCIe 4: Unconnected
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 54: PCIe 5 MARVELL IDE State: on
Comment: PCIe 5: Marvell 88SE6121 IDE/SATA controller
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 55: PCIe 6 ethernet NIC State: on
Comment: PCIe 6: Atheros AR8121 Ethernet NIC
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 89: irq 0xe5 = 0x02 #Need to test with 0x82 value You can drop this line entirely. Register 0xe4 is setting all GPIOs as input except for GPIO82. This means that only bit 2 of register 0xe5 is writeable, and it defaults to zero already.
Ivan Vatlin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 18:
(8 comments)
https://review.coreboot.org/c/coreboot/+/38143/18/Documentation/mainboard/as... File Documentation/mainboard/asus/p5q.md:
https://review.coreboot.org/c/coreboot/+/38143/18/Documentation/mainboard/as... PS18, Line 66: model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2)
Nit: use capitals for names […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... File src/mainboard/asus/p5qc/variants/p5q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 50: PCIe 1 slot 1
State: on […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 51: PCIe 2 slot 2
State: on […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 52: PCIe 3 slot 3
State: off […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 53: PCIe 4 (Silicon Image?)
State: off […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 54: PCIe 5 MARVELL IDE
State: on […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 55: PCIe 6 ethernet NIC
State: on […]
Ack
https://review.coreboot.org/c/coreboot/+/38143/18/src/mainboard/asus/p5qc/va... PS18, Line 89: irq 0xe5 = 0x02 #Need to test with 0x82 value
You can drop this line entirely. Register 0xe4 is setting all GPIOs as input except for GPIO82. […]
Ack
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38143
to look at the new patch set (#19).
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 207 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38143/19
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 19: Code-Review+2
Perfect, thank you!
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin jenrus@tuta.io Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- A Documentation/mainboard/asus/p5q.md M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q/devicetree.cb 4 files changed, 207 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/asus/p5q.md b/Documentation/mainboard/asus/p5q.md new file mode 100644 index 0000000..bce71e8 --- /dev/null +++ b/Documentation/mainboard/asus/p5q.md @@ -0,0 +1,77 @@ +# ASUS P5Q + +This page describes how to run coreboot on the [ASUS P5Q] desktop board. + +## TODO + +The following things are working in this coreboot port: + ++ PCI slots ++ PCI-e slots ++ Onboard Ethernet ++ USB ++ Onboard sound card ++ PS/2 keyboard ++ All 4 DIMM slots ++ S3 suspend and resume ++ Red SATA ports + +The following things are still missing from this coreboot port: + ++ PS/2 mouse support ++ PATA aka IDE (because of buggy IDE controller) ++ Fan control (will be working on 100% power) ++ TPM module (support not implemented) + +The following things are untested on this coreboot port: + ++ S/PDIF ++ CD Audio In ++ Floppy disk drive ++ FireWire: PCI device shows up and driver loads, no further test + + +## Flashing coreboot + +```eval_rst ++-------------------+----------------+ +| Type | Value | ++===================+================+ +| Socketed flash | Yes | ++-------------------+----------------+ +| Model | MX25L8005 | ++-------------------+----------------+ +| Size | 1 MiB | ++-------------------+----------------+ +| Package | Socketed DIP-8 | ++-------------------+----------------+ +| Write protection | No | ++-------------------+----------------+ +| Dual BIOS feature | No | ++-------------------+----------------+ +| Internal flashing | Yes | ++-------------------+----------------+ +``` + +You can flash coreboot into your motherboard using [this guide]. + +## Technology + +```eval_rst ++------------------+---------------------------------------------------+ +| Northbridge | Intel P45 (called x4x in coreboot code) | ++------------------+---------------------------------------------------+ +| Southbridge | Intel ICH10R (called i82801jx in coreboot code) | ++------------------+---------------------------------------------------+ +| CPU (LGA775) | Model f4x, f6x, 6fx, 1067x (Pentium 4, d, Core 2) | ++------------------+---------------------------------------------------+ +| SuperIO | Winbond W83667HG | ++------------------+---------------------------------------------------+ +| Coprocessor | No | ++------------------+---------------------------------------------------+ +| Clockgen (CK505) | ICS 9LPRS918JKLF | ++------------------+---------------------------------------------------+ +``` + +[ASUS P5Q]: https://www.asus.com/Motherboards/P5Q +[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index b59cd3c..e7d23bd 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -1,8 +1,9 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com # Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# Copyright (C) 2019 Ivan Vatlin jenrus@tuta.io # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ # GNU General Public License for more details. #
-if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO +if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -38,12 +39,14 @@ default "p5qc" if BOARD_ASUS_P5QC default "p5q_pro" if BOARD_ASUS_P5Q_PRO default "p5ql_pro" if BOARD_ASUS_P5QL_PRO + default "p5q" if BOARD_ASUS_P5Q
config MAINBOARD_PART_NUMBER string default "P5QC" if BOARD_ASUS_P5QC default "P5Q PRO" if BOARD_ASUS_P5Q_PRO default "P5QL PRO" if BOARD_ASUS_P5QL_PRO + default "P5Q" if BOARD_ASUS_P5Q
config DEVICETREE string diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name index 2a35036..22c0cca 100644 --- a/src/mainboard/asus/p5qc/Kconfig.name +++ b/src/mainboard/asus/p5qc/Kconfig.name @@ -6,3 +6,6 @@
config BOARD_ASUS_P5QL_PRO bool "P5QL PRO" + +config BOARD_ASUS_P5Q + bool "P5Q" diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb new file mode 100644 index 0000000..a1211cc --- /dev/null +++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb @@ -0,0 +1,122 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# Copyright (C) 2019 Ivan Vatlin jenrus@tuta.io +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 on end # PEG + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Enable all six SATA ports. + register "sata_port_map" = "0x3f" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + + device pci 19.0 off end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1: PCIEX1_1 slot + device pci 1c.1 on end # PCIe 2: PCIEX1_2 slot + device pci 1c.2 off end # PCIe 3: Unconnected + device pci 1c.3 off end # PCIe 4: Unconnected + device pci 1c.4 on end # PCIe 5: Marvell 88SE6121 IDE/SATA controller + device pci 1c.5 on end # PCIe 6: Atheros AR8121 Ethernet NIC + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83667hg-a # Super I/O + device pnp 2e.0 on # FDC + # Global registers + irq 0x2a = 0x00 + irq 0x2c = 0x22 + irq 0x2d = 0x00 + # Floppy + io 0x60 = 0x3f0 + irq 0xf0 = 0x0e + end + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off end # SPI1 + device pnp 2e.107 off end # GPIO6 + device pnp 2e.207 off end # GPIO7 + device pnp 2e.307 on # GPIO8 + irq 0xe4 = 0xfb + end + device pnp 2e.407 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xfe = 0x07 + end + device pnp 2e.309 on end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # 3VSBSW# enable + irq 0xe5 = 0x02 + irq 0xf2 = 0xfc + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 0 + # IRQ purposefully not assigned to prevent lockups + end + device pnp 2e.c on end # PECI + device pnp 2e.d on end # VID_BUSSEL + device pnp 2e.f on end # GPIO_PP_OD + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end # SATA (legacy mode) + device pci 1f.6 off end + end + end +end
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 20: Code-Review+1
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38143 )
Change subject: mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation) ......................................................................
Patch Set 20:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/210 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/209 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/208
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Arthur Heymans (Code Review)
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Ivan Vatlin (Code Review)
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Jenrus (Джэнрус) (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)