[XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL - coreboot-gerrit

3 Sep 2024


      Attention is currently required from: Saurabh Mishra.
Pratikkumar V Prajapati has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84178?usp=email )
Change subject: soc/intel/common/block: Include register offsets for POWER_CTL
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Patch Set 4: Code-Review+2
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Gerrit-Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Gerrit-Change-Number: 84178
Gerrit-PatchSet: 4
Gerrit-Owner: Saurabh Mishra mishra.saurabh@intel.com
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