Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80548?usp=email )
Change subject: soc/intel/xeon_sp: Align resources to 4K
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Patch Set 1:
(2 comments)
Patchset:
PS1:
one more question is: what if we without this change? would there be any errors or confusing behavio […]
Yes, it would take the BAR enable bit as address and thus be of by one.
File src/soc/intel/xeon_sp/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/80548/comment/d4e46634_5a18a3d4 :
PS1, Line 14: #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 10, desc_)
Mask bit 10 equals to 1K. I believe we would like to use 4K, right? […]
Good catch!
Updated to 12 bits and thus aligning to 4K.
The reason is not to align with the page size, but the minimal alignment used by all BARs. Here the VTBAR has the lowest alignment.
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