Change in coreboot[master]: mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51351 )

Change subject: mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag
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mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag

Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index eb7be69..d0cb5f1 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -14,6 +14,9 @@

# FSP configuration

+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
    register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
    register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
    register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
@@ -212,7 +215,6 @@
    	device pci 0e.0 off end # VMD
    	device pci 10.0 off end
    	device pci 10.1 off end
-		device pci 10.2 on  end # CNVi: BT
    	device pci 10.6 off end # THC0
    	device pci 10.7 off end # THC1
    	device pci 11.0 off end