[S] Change in coreboot[main]: soc/intel/adl: Don't set up SPD on LPDDRx

[Arthur Heymans (Code Review)]

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84205?usp=email )

Change subject: soc/intel/adl: Don't set up SPD on LPDDRx
......................................................................

soc/intel/adl: Don't set up SPD on LPDDRx

The common code for SPD is invalid for LPDDRx, so don't call it as it is
not needed.

Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 11 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84205/1

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 35c3252..16ba9ff 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -236,7 +236,7 @@
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
    	 const struct mem_spd *spd_info, bool half_populated)
 {
-	struct mem_channel_data data;
+	struct mem_channel_data data = {};
    bool dq_dqs_auto_detect = false;
    FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;

@@ -253,14 +253,17 @@
    /* Fill LpDdrrDqDqs Retraining for memory */
    mem_cfg->LpDdrDqDqsReTraining = mb_cfg->LpDdrDqDqsReTraining;

+	bool has_spd;
    switch (mb_cfg->type) {
    case MEM_TYPE_DDR4:
    	meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
    	dq_dqs_auto_detect = true;
+		has_spd = true;
    	break;
    case MEM_TYPE_DDR5:
    	meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
    	dq_dqs_auto_detect = true;
+		has_spd = true;
    	/*
    	* TODO: Drop this workaround once SMBus driver in coreboot is updated to
    	* support DDR5 EEPROM reading.
@@ -272,17 +275,21 @@
    	break;
    case MEM_TYPE_LP4X:
    	meminit_lp4x(mem_cfg);
+		has_spd = false;
    	break;
    case MEM_TYPE_LP5X:
    	meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
+		has_spd = false;
    	break;
    default:
    	die("Unsupported memory type(%d)\n", mb_cfg->type);
    }

-	mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated,
-			&data);
-	mem_init_spd_upds(mem_cfg, &data);
+	if (has_spd) {
+		mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info,
+					  half_populated, &data);
+		mem_init_spd_upds(mem_cfg, &data);
+	}
    mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
    mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
 }