Change in coreboot[master]: soc/intel/braswell: Prevent NULL pointer dereference

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49359 )

Change subject: soc/intel/braswell: Prevent NULL pointer dereference
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soc/intel/braswell: Prevent NULL pointer dereference

Exit early if the chipset power state info isn't in CBMEM. Return -1 in
order to ensure the one caller of this function exits early as well.

Found-by: Coverity CID 1442304
Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49359
Reviewed-by: Arthur Heymans 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Paul Menzel 
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/braswell/ramstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Arthur Heymans: Looks good to me, approved
  Lance Zhao: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 7b92c52..de90cb7 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -125,6 +125,9 @@
    struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
    static uint32_t gpe0_sts;

+	if (!ps)
+		return -1;
+
    *pm1 = ps->pm1_sts & ps->pm1_en;

gpe0_sts = ps->gpe0_sts & ps->gpe0_en;