[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled

[Johnny Lin (Code Review)]

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Jingle Hsu, David Hendricks, Shuo Liu, Nill Ge, Arthur Heymans, Lean Sheng Tan, TangYiwei, Shelly Chang, Tim Chu.

Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Paul Menzel, Jingle Hsu, David Hendricks, Nill Ge, Arthur Heymans, TangYiwei, Christian Walter, Shuo Liu, Lean Sheng Tan, Shelly Chang, Tim Chu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74296

to look at the new patch set (#3).

Change subject: soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
......................................................................

soc/intel/xeon_sp: Fix very small total memory when CXL is enabled

Processor attached memory should use ram_from_to rather than
reserved_ram_from_to. Treat the calculation of gi_mem_size size as
64MB.
By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
this should fix small total memory issue.

Tested=On AC without attaching CXL memory, the total memory size is
the same as de-selecting SOC_INTEL_HAS_CXL.

Change-Id: I38e9d138fd284620ac616a65f444e943f1774869
Signed-off-by: Johnny Lin 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 32 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/74296/3