Attention is currently required from: Hung-Te Lin, Paul Menzel, Xi Chen, Yidi Lin, Yu-Ping Wu.
Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83925?usp=email )
Change subject: soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA ......................................................................
Patch Set 12:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83925/comment/dfaf3f2e_fc0b6974?usp... : PS8, Line 7: mmu
MMU
Done
https://review.coreboot.org/c/coreboot/+/83925/comment/5287ef83_90ee129b?usp... : PS8, Line 16:
Please elaborate why the common implementation [1] can’t be used. […]
because the disable cache flow is different from the previous chips.
https://review.coreboot.org/c/coreboot/+/83925/comment/f501c3c1_14e48313?usp... : PS8, Line 17: TEST=build pass
Any way to test it on hardware yet?
Done
File src/soc/mediatek/mt8196/l2c_ops.c:
https://review.coreboot.org/c/coreboot/+/83925/comment/cd08872c_f6a26ad7?usp... : PS8, Line 36: } while (((v >> CLUST_DIS_SHIFT) & CLUST_DIS_VAL) != CLUST_DIS_VAL);
Could this be an infinite loop, or is it guaranteed to finish?
will finish, verified
File src/soc/mediatek/mt8196/l2c_ops.c:
https://review.coreboot.org/c/coreboot/+/83925/comment/b0fc0e52_4e682781?usp... : PS10, Line 11: FULLnHALF
UPPER_CASE please.
Done