[M] Change in coreboot[master]: soc/intel/: Store CSE firmware version into cbmem table

[Dinesh Gehlot (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik.

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74256 )

Change subject: soc/intel/: Store CSE firmware version into cbmem table
......................................................................

soc/intel/: Store CSE firmware version into cbmem table

The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called either from RAMSTAGE or ROMSTAGE
based on underlying platform.

BUG=b:273661726

Signed-off-by: Dinesh Gehlot 
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 60 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/1

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index fa5c8d9..4162d84 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -85,6 +85,7 @@
 #define CBMEM_ID_MEM_CHIP_INFO	0x5048434D
 #define CBMEM_ID_AMD_STB	0x5f425453
 #define CBMEM_ID_AMD_MP2	0x5f32504d
+#define CBMEM_ID_CSE_PARTITION_VERSION 0x43535056

#define CBMEM_ID_TO_NAME_TABLE				 \
    { CBMEM_ID_ACPI,		"ACPI       " }, \
@@ -163,5 +164,6 @@
    { CBMEM_ID_TYPE_C_INFO,		"TYPE_C INFO"},\
    { CBMEM_ID_MEM_CHIP_INFO,       "MEM CHIP INFO"},\
    { CBMEM_ID_AMD_STB,		"AMD STB"},\
-	{ CBMEM_ID_AMD_MP2,		"AMD MP2 BUFFER"}
+	{ CBMEM_ID_AMD_MP2,		"AMD MP2 BUFFER"},\
+	{ CBMEM_ID_CSE_PARTITION_VERSION, "CSE PARTITION VERSION"}
 #endif /* _CBMEM_ID_H_ */
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index a3273e6..ff013d9 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -231,4 +231,7 @@

if (CONFIG(ENABLE_EARLY_DMA_PROTECTION))
    	vtd_enable_dma_protection();
+
+	if (CONFIG(ENV_ROMSTAGE) && CONFIG(DRIVERS_INTEL_ISH))
+		store_cse_rw_fw_version();
 }
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 4a624e6..949e057 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1077,6 +1077,24 @@
    return handle_cse_sub_part_fw_update_rv(rv);
 }

+void store_cse_rw_fw_version(void)
+{
+	if (vboot_recovery_mode_enabled() || !CONFIG(SOC_INTEL_CSE_LITE_SKU))
+		return;
+
+	struct get_bp_info_rsp cse_bp_info;
+
+	if (!cse_get_bp_info(&cse_bp_info))
+			return;
+
+	const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info);
+	struct cse_fw_partition_info *version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version));
+	version->cur_cse_fw_version.major = cse_bp->fw_ver.major;
+	version->cur_cse_fw_version.minor = cse_bp->fw_ver.minor;
+	version->cur_cse_fw_version.hotfix = cse_bp->fw_ver.hotfix;
+	version->cur_cse_fw_version.build = cse_bp->fw_ver.build;
+}
+
 void cse_fw_sync(void)
 {
    static struct get_bp_info_rsp cse_bp_info;
@@ -1161,6 +1179,9 @@
    	timestamp_add_now(TS_CSE_FW_SYNC_START);
    	cse_fw_sync();
    	timestamp_add_now(TS_CSE_FW_SYNC_END);
+
+		if (CONFIG(ENV_RAMSTAGE) && CONFIG(DRIVERS_INTEL_ISH))
+			store_cse_rw_fw_version();
    }
 }

diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index adb4f6e..2866343 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -143,6 +143,18 @@
    struct flash_partition_data manifest_data;
 };

+/* ISHC version */
+struct cse_fw_ish_version_info {
+	struct fw_version prev_cse_fw_version;
+	struct fw_version cur_ish_fw_version;
+};
+
+/* CSE and ISHC version */
+struct cse_fw_partition_info {
+	struct fw_version cur_cse_fw_version;
+	struct cse_fw_ish_version_info ish_partition_info;
+};
+
 /* CSE RX and TX error status */
 enum cse_tx_rx_status {
    /*
@@ -431,6 +443,11 @@
 uint8_t cse_wait_com_soft_temp_disable(void);

/*
+ * This API stores current CSE firmware version to CBMEM memory, except during recovery mode.
+ */
+void store_cse_rw_fw_version(void);
+
+/*
  * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
  * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
  * boot from RW and triggers recovery mode if CSE fails to jump to RW.