[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons, Yidi Lin.

Hello Hung-Te Lin, build bot (Jenkins), Bayi Cheng, Angel Pons, Yu-Ping Wu, Yidi Lin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68659

to look at the new patch set (#5).

Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
......................................................................

soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz

According to the datasheet, the maximum frequency supported by
W25Q64JWZPIM (Winbond) is 50MHz. To meet this restriction, we lower
the NOR clock from 52MHz to 39MHz which is the closest frequency
of the next clock level on MT8186.

This adds about 15ms to boot time.

BUG=b:253167106
TEST=emerge-corsola coreboot.
BRANCH=corsola

Signed-off-by: Dandan He 
Signed-off-by: Bayi Cheng 
Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd
---
M src/soc/mediatek/mt8186/pll.c
1 file changed, 23 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/68659/5