[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )

(

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................

soc/intel/common/gpio: support 16-bit CPU Port ID

- Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID.
- Change cpu_port field to 16-bit width if the Kconfig is set.

BUG=none
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field. The bit 15:8 of the returned port ID value should be 0xF2
instead of zero.

Signed-off-by: Cliff Huang 
Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/include/intelblocks/gpio.h
2 files changed, 15 insertions(+), 1 deletion(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig
index de0546c..60a5967 100644
--- a/src/soc/intel/common/block/gpio/Kconfig
+++ b/src/soc/intel/common/block/gpio/Kconfig
@@ -63,4 +63,14 @@
     SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser
     is 4 bits to support Native Function 1 to 15.

+config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID
+	bool
+	default n
+	help
+	  Enable support for 16-bit CPU Port IDs.
+	  Intel SoCs (starting with Panther Lake) have extended the CPU Port ID field
+	  to 16 bits.
+	  Enable this option if your platform requires the GPIO driver to
+	  accommodate this larger Port ID value.
+
 endif
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 8e60a16..39d17a1 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -136,7 +136,11 @@
    uint8_t		gpi_status_offset;  /* specifies offset in struct
    					gpi_status */
    uint8_t		port;	/* PCR Port ID */
-	uint8_t		cpu_port; /* CPU Port ID */
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID)
+	uint16_t	cpu_port; /* Use 16-bit CPU Port ID */
+#else
+	uint8_t	cpu_port; /* Use 8-bit CPU Port ID */
+#endif
    const struct reset_mapping	*reset_map; /* PADRSTCFG logical to
    		chipset mapping */
    size_t		num_reset_vals;