Attention is currently required from: Alicja Michalska, David Milosevic, Michał Żygowski.
Felix Held has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/84213?usp=email )
Change subject: mainboard/hardkernel: Add ODROID H4+ initial support ......................................................................
Patch Set 2:
(7 comments)
File src/mainboard/hardkernel/odroid_h4/Kconfig:
https://review.coreboot.org/c/coreboot/+/84213/comment/891c6be7_52f12daa?usp... : PS2, Line 17: in order to have aspm enabled, the following kconfig selects are probably needed: select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE
https://review.coreboot.org/c/coreboot/+/84213/comment/47d1d56e_f756cffe?usp... : PS2, Line 24: config MAINBOARD_VENDOR : default "HARDKERNEL" already specified in the mainboard vendor kconfig, so this can be dropped here
https://review.coreboot.org/c/coreboot/+/84213/comment/6c0fa9e4_8493e1e5?usp... : PS2, Line 27: config MAINBOARD_FAMILY : default "Default String" is this needed?
File src/mainboard/hardkernel/odroid_h4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/84213/comment/2f2160d8_d559f7bf?usp... : PS2, Line 26: device cpu_cluster 0 on end this line isn't needed, since the chipset devicetree already has that one
https://review.coreboot.org/c/coreboot/+/84213/comment/254e92e7_2f326ce0?usp... : PS2, Line 67: register "usb3_ports[9]" = "USB3_PORT_EMPTY" there are more usb2_ports and usb3_ports entries in here than the soc has usb 2/3 ports; i'd drop the entries for the ones that aren't available on the hardware; iirc adl-n has 8 usb2 ports and up to 4 usb3 ports on the pch
https://review.coreboot.org/c/coreboot/+/84213/comment/46c978d3_9b653a53?usp... : PS2, Line 163: .clk_req = 3, this soc input is connected to ground, so i wonder if this should be replaced by .flags = PCIE_RP_CLK_REQ_UNUSED
File src/mainboard/hardkernel/odroid_h4/gpio.c:
https://review.coreboot.org/c/coreboot/+/84213/comment/686698d4_01c65e30?usp... : PS2, Line 8: #define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ shouldn't this go into one of the soc's gpio header files?