Ravi Mistry has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69320 )
Change subject: mb: Add HP Memphis-S (IPM87-MP) ......................................................................
mb: Add HP Memphis-S (IPM87-MP)
This is a µATX mainboard with an LGA1150 socket and two DDR3 DIMM slots.
Specs: - HP Memphis-S (IPM87-MP) - Intel H87 - Macronix MX25L6473E (8MB) - Fintek F71808A - Realtek RTL8111 compatible Gigabit
Tested with EDK2 payload to boot Fedora Linux 36.
Working: - PCIE slots (including MINI_CARD1) - USB 2.0, 3.0 - Both DIMM slots - SATA (except mSATA) - Ethernet - VGA, DVI (libgfxinit and VBT) - S0/S3/S5 - Audio - Hardware monitor
Untested: - mSATA - HOOD_SENSE - MINI_LED header - EHCI debug port, LPC debug - CMOS
Change-Id: If3162fa4c60374877d9e67e9e1f6121743f03b21 Signed-off-by: Ravi Mistry rvstry@protonmail.com --- A src/mainboard/hp/memphis-s/Kconfig A src/mainboard/hp/memphis-s/Kconfig.name A src/mainboard/hp/memphis-s/Makefile.inc A src/mainboard/hp/memphis-s/acpi/ec.asl A src/mainboard/hp/memphis-s/acpi/platform.asl A src/mainboard/hp/memphis-s/acpi/superio.asl A src/mainboard/hp/memphis-s/board_info.txt A src/mainboard/hp/memphis-s/bootblock.c A src/mainboard/hp/memphis-s/cmos.default A src/mainboard/hp/memphis-s/cmos.layout A src/mainboard/hp/memphis-s/data.vbt A src/mainboard/hp/memphis-s/devicetree.cb A src/mainboard/hp/memphis-s/dsdt.asl A src/mainboard/hp/memphis-s/gma-mainboard.ads A src/mainboard/hp/memphis-s/gpio.c A src/mainboard/hp/memphis-s/hda_verb.c A src/mainboard/hp/memphis-s/romstage.c 17 files changed, 650 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69320/1
diff --git a/src/mainboard/hp/memphis-s/Kconfig b/src/mainboard/hp/memphis-s/Kconfig new file mode 100644 index 0000000..a67209d0 --- /dev/null +++ b/src/mainboard/hp/memphis-s/Kconfig @@ -0,0 +1,35 @@ +if BOARD_HP_MEMPHIS_S + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_FINTEK_F71808A + select NO_UART_ON_SUPERIO + +config MAINBOARD_DIR + string + default "hp/memphis-s" + +config MAINBOARD_PART_NUMBER + string + default "Memphis-S" + +config VGA_BIOS_ID + string + default "8086,0412" + +#config USBDEBUG_HCD_INDEX +# int +# default 2 +# This board has an EHCI debug port that has not yet been tested +endif diff --git a/src/mainboard/hp/memphis-s/Kconfig.name b/src/mainboard/hp/memphis-s/Kconfig.name new file mode 100644 index 0000000..8268d31 --- /dev/null +++ b/src/mainboard/hp/memphis-s/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_MEMPHIS_S + bool "Memphis-S" diff --git a/src/mainboard/hp/memphis-s/Makefile.inc b/src/mainboard/hp/memphis-s/Makefile.inc new file mode 100644 index 0000000..d9a8d18 --- /dev/null +++ b/src/mainboard/hp/memphis-s/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/hp/memphis-s/acpi/ec.asl b/src/mainboard/hp/memphis-s/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/memphis-s/acpi/ec.asl diff --git a/src/mainboard/hp/memphis-s/acpi/platform.asl b/src/mainboard/hp/memphis-s/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/hp/memphis-s/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/hp/memphis-s/acpi/superio.asl b/src/mainboard/hp/memphis-s/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/memphis-s/acpi/superio.asl diff --git a/src/mainboard/hp/memphis-s/board_info.txt b/src/mainboard/hp/memphis-s/board_info.txt new file mode 100644 index 0000000..ff5c890 --- /dev/null +++ b/src/mainboard/hp/memphis-s/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2014 + diff --git a/src/mainboard/hp/memphis-s/bootblock.c b/src/mainboard/hp/memphis-s/bootblock.c new file mode 100644 index 0000000..4801fc9 --- /dev/null +++ b/src/mainboard/hp/memphis-s/bootblock.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f71808a/f71808a.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define KEYBOARD_DEV PNP_DEV(0x2e, F71808A_KBC) +#define ACPI_DEV PNP_DEV(0x2e, F71808A_PME) + +void mainboard_config_superio(void) +{ + pnp_enter_conf_state(GLOBAL_DEV); + + pnp_write_config(GLOBAL_DEV, 0x25, 0x02); + pnp_write_config(GLOBAL_DEV, 0x27, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + + pnp_set_logical_device(KEYBOARD_DEV); + pnp_write_config(KEYBOARD_DEV, 0xfe, 0x81); + +/* GPIO register 0xe2, ACPI register 0xf1 values (0x1f and 0x60) */ +/* don't match values using vendor firmware (0x1d and 0x00), */ +/* but nothing appears to be wrong */ + +/* HWM register 0x21 (expected value 0xd6, actual value 0xd5) */ + + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe0, 0x00); + pnp_write_config(ACPI_DEV, 0xe1, 0xc6); + pnp_write_config(ACPI_DEV, 0xe8, 0x6f); + pnp_write_config(ACPI_DEV, 0xed, 0xc0); + pnp_write_config(ACPI_DEV, 0xf0, 0xf2); + pnp_write_config(ACPI_DEV, 0xf1, 0x00); + pnp_write_config(ACPI_DEV, 0xf2, 0x13); + pnp_write_config(ACPI_DEV, 0xf8, 0x04); + pnp_write_config(ACPI_DEV, 0xf9, 0x01); + + pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/hp/memphis-s/cmos.default b/src/mainboard/hp/memphis-s/cmos.default new file mode 100644 index 0000000..c51001c --- /dev/null +++ b/src/mainboard/hp/memphis-s/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/hp/memphis-s/cmos.layout b/src/mainboard/hp/memphis-s/cmos.layout new file mode 100644 index 0000000..c9ba76c --- /dev/null +++ b/src/mainboard/hp/memphis-s/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/hp/memphis-s/data.vbt b/src/mainboard/hp/memphis-s/data.vbt new file mode 100644 index 0000000..069abc6 --- /dev/null +++ b/src/mainboard/hp/memphis-s/data.vbt Binary files differ diff --git a/src/mainboard/hp/memphis-s/devicetree.cb b/src/mainboard/hp/memphis-s/devicetree.cb new file mode 100644 index 0000000..8b09ab5 --- /dev/null +++ b/src/mainboard/hp/memphis-s/devicetree.cb @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "usb_xhci_on_resume" = "true" + register "ec_present" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gpe0_en_1" = "0x46" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x8" + device pci 14.0 on # xHCI Controller + subsystemid 0x103c 0x2af7 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x2af7 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x2af7 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x103c 0x2af7 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x2af7 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIE_X1_1 + end + device pci 1c.3 on # PCIE_X1_2 + end + device pci 1c.4 on # PCIE_X1_3 + end + device pci 1c.5 on # MINI_CARD1 + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x103c 0x2af7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x2af7 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x103c 0x2af7 + chip superio/fintek/f71808a + register "multi_function_register_0" = "0x00" + register "multi_function_register_1" = "0x80" + register "multi_function_register_2" = "0x21" + register "multi_function_register_3" = "0x4f" + register "multi_function_register_4" = "0x1c" + register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x5c" # TCC temperature = 92 °C + register "hwm_fan1_boundary_hysteresis" = "0x44" + register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100% + register "hwm_fan1_seg2_speed" = "0xff" # Fan 1 segment 2 = 100% + register "hwm_fan1_seg3_speed" = "0x93" # Fan 1 segment 3 = 58% + register "hwm_fan1_seg4_speed" = "0x7f" # Fan 1 segment 4 = 50% + register "hwm_fan1_seg5_speed" = "0x5b" # Fan 1 segment 5 = 36% + register "hwm_fan1_temp_src" = "0x1c" # Fan 1 source = PECI + register "hwm_vt1_boundary_1_temperature" = "0x61" # Fan 1 boundary 1 = 97°C + register "hwm_vt1_boundary_2_temperature" = "0x5c" # Fan 1 boundary 2 = 92°C + register "hwm_vt1_boundary_3_temperature" = "0x3c" # Fan 1 boundary 3 = 60°C + register "hwm_vt1_boundary_4_temperature" = "0x2d" # Fan 1 boundary 4 = 45°C + register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xff" # Fan 2 segment 2 = 100% + register "hwm_fan2_seg3_speed" = "0x7f" # Fan 2 segment 3 = 50% + register "hwm_fan2_seg4_speed" = "0x72" # Fan 2 segment 4 = 45% + register "hwm_fan2_seg5_speed" = "0x5b" # Fan 2 segment 5 = 36% + register "hwm_fan2_temp_src" = "0x1c" # Fan 2 source = PECI + register "hwm_vt2_boundary_1_temperature" = "0x61" # Fan 2 boundary 1 = 97°C + register "hwm_vt2_boundary_2_temperature" = "0x5c" # Fan 2 boundary 2 = 92°C + register "hwm_vt2_boundary_3_temperature" = "0x3c" # Fan 2 boundary 3 = 60°C + register "hwm_vt2_boundary_4_temperature" = "0x2d" # Fan 2 boundary 4 = 45°C + device pnp 2e.1 off end # COM1 + device pnp 2e.4 on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0x00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 0x01 + irq 0x72 = 0x0c + end + device pnp 2e.6 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.7 off end # WDT + device pnp 2e.8 off end # CIR + device pnp 2e.a on # PME, ACPI, EUP + end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x103c 0x2af7 + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x2af7 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Desktop Host bridge + subsystemid 0x103c 0x2af7 + end + device pci 01.0 on # PCIE_X16 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x2af7 + end + device pci 03.0 off # Mini-HD audio + end + end +end diff --git a/src/mainboard/hp/memphis-s/dsdt.asl b/src/mainboard/hp/memphis-s/dsdt.asl new file mode 100644 index 0000000..13a5b6a --- /dev/null +++ b/src/mainboard/hp/memphis-s/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/memphis-s/gma-mainboard.ads b/src/mainboard/hp/memphis-s/gma-mainboard.ads new file mode 100644 index 0000000..c9e4326 --- /dev/null +++ b/src/mainboard/hp/memphis-s/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/memphis-s/gpio.c b/src/mainboard/hp/memphis-s/gpio.c new file mode 100644 index 0000000..042d9af --- /dev/null +++ b/src/mainboard/hp/memphis-s/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio35 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/memphis-s/hda_verb.c b/src/mainboard/hp/memphis-s/hda_verb.c new file mode 100644 index 0000000..4de0104 --- /dev/null +++ b/src/mainboard/hp/memphis-s/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76f3, /* Codec Vendor / Device ID: IDT */ + 0x103c2af7, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c2af7), + AZALIA_PIN_CFG(0, 0x0a, 0x0221402f), + AZALIA_PIN_CFG(0, 0x0b, 0x01114020), + AZALIA_PIN_CFG(0, 0x0c, 0x02a19041), + AZALIA_PIN_CFG(0, 0x0e, 0x01a1904e), + AZALIA_PIN_CFG(0, 0x0f, 0x01813050), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x24, 0x40f000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/memphis-s/romstage.c b/src/mainboard/hp/memphis-s/romstage.c new file mode 100644 index 0000000..143b8c6 --- /dev/null +++ b/src/mainboard/hp/memphis-s/romstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};
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Ravi Mistry (Code Review)