Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75555?usp=email )
Change subject: mb/google/rex,screebo: Update GPIO PAD IO Standby State ......................................................................
mb/google/rex,screebo: Update GPIO PAD IO Standby State
Fix for the "Onboard Keyboard and Type-C ports are not working after resuming from powerd_dbus_suspend" issue. This issue was caused since FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState programming when GpioOverride UPD is enabled.
This patch moves the IO Standby State programming that FSP was doing to coreboot.
BUG=b:284264580 TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C
Signed-off-by: Bora Guvendik bora.guvendik@intel.com Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555 Reviewed-by: Kapil Porwal kapilporwal@google.com Reviewed-by: Subrata Banik subratabanik@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/rex/variants/rex0/gpio.c M src/mainboard/google/rex/variants/screebo/gpio.c 2 files changed, 32 insertions(+), 16 deletions(-)
Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 1ebf07e..b30bff4 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -15,13 +15,20 @@
/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ - /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ - /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ - /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ - /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ - /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ - /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R */ + PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R */ + PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R */ + PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R */ + PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L */ + PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R */ + PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L */ + PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE), /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPP_A12 : [] ==> EN_UCAM_PWR */ @@ -32,7 +39,8 @@ PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG), /* GPP_A15 : [] ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_A15, 1, DEEP), - /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */ + /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L */ + PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c index f31506c..a9d4593 100644 --- a/src/mainboard/google/rex/variants/screebo/gpio.c +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -8,13 +8,20 @@
/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ - /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ - /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ - /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ - /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ - /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ - /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R */ + PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R */ + PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R */ + PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R */ + PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L */ + PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R */ + PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L */ + PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE), /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPP_A12 : [] ==> EN_UCAM_PWR */ @@ -25,7 +32,8 @@ PAD_NC(GPP_A14, NONE), /* GPP_A15 : net NC is not present in the given design */ PAD_NC(GPP_A15, NONE), - /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */ + /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L */ + PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-
Martin L Roth (Code Review)