Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Jianjun Wang (Code Review)]

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu.
Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
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Patch Set 18:

(1 comment)

Patchset:

PS9:
> Can we start out with mmio_base and size?  Those seem very generic.  Is MTK deriving the mmio_size from the ctrl_base?  QC can derive the atu_base in their QC specific case separately.

It's more like the ’ctrl_base‘ for MTK's SoCs, since it's the base address of the PCIe controller, and we have the MMIO space start from 0x2000_0000 [1] for accessing the BAR of PCIe devices.
[1] https://review.coreboot.org/c/coreboot/+/62360/28/src/mainboard/google/cherr...