Change in coreboot[master]: src: use mca_clear_status function instead of open coding

[Felix Held (Code Review)]

Attention is currently required from: Patrick Rudolph.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56259 )

Change subject: src: use mca_clear_status function instead of open coding
......................................................................

src: use mca_clear_status function instead of open coding

Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400
Signed-off-by: Felix Held 
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/intel/common/block/cpu/cpulib.c
9 files changed, 11 insertions(+), 68 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56259/1

diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 76c8521..369ed5a 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -17,7 +17,6 @@
 {
    u8 i;
    msr_t msr;
-	unsigned int num_banks;
    int msrno;
 #if CONFIG(LOGICAL_CPUS)
    u32 siblings;
@@ -59,11 +58,7 @@
    x86_enable_cache();

/* zero the machine check error status registers */
-	num_banks = mca_get_bank_count();
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
+	mca_clear_status();

/* Enable the local CPU APICs */
    setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 883bd59..356647a 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -20,7 +20,6 @@

u8 i;
    msr_t msr;
-	unsigned int num_banks;
    int msrno;
    unsigned int cpu_idx;
 #if CONFIG(LOGICAL_CPUS)
@@ -58,11 +57,7 @@
    x86_enable_cache();

/* zero the machine check error status registers */
-	num_banks = mca_get_bank_count();
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
+	mca_clear_status();

/* Enable the local CPU APICs */
    setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index f945f80..f01f840 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -19,7 +19,6 @@

u8 i;
    msr_t msr;
-	unsigned int num_banks;
    int msrno;
 #if CONFIG(LOGICAL_CPUS)
    u32 siblings;
@@ -56,11 +55,7 @@
    x86_enable_cache();

/* zero the machine check error status registers */
-	num_banks = mca_get_bank_count();
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
+	mca_clear_status();

/* Enable the local CPU APICs */
    setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 3c78c09..07836fc 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -22,7 +22,6 @@

u8 i;
    msr_t msr;
-	unsigned int num_banks;
    u32 siblings;

/*
@@ -41,11 +40,7 @@
    x86_mtrr_check();

/* zero the machine check error status registers */
-	num_banks = mca_get_bank_count();
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
+	mca_clear_status();

/* Enable the local CPU APICs */
    setup_lapic();
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 29c663e..2c6384c 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -527,12 +527,10 @@
    for (i = 0; i < num_banks; i++)
    	wrmsr(IA32_MC_CTL(i), msr);

-	msr.lo = msr.hi = 0;
    /* TODO(adurbin): This should only be done on a cold boot. Also, some
     * of these banks are core vs package scope. For now every CPU clears
     * every bank. */
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
+	mca_clear_status();
 }

/* All CPUs including BSP will run the following function. */
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index fe5ac56..f70d7b2 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -73,24 +73,13 @@
           ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK);
 }

-static void configure_mca(void)
-{
-	msr_t msr;
-	int i;
-	const unsigned int num_banks = mca_get_bank_count();
-
-	msr.lo = msr.hi = 0;
-	/* This should only be done on a cold boot */
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
-}
-
 static void model_2065x_init(struct device *cpu)
 {
    char processor_name[49];

/* Clear out pending MCEs */
-	configure_mca();
+	/* This should only be done on a cold boot */
+	mca_clear_status();

/* Print processor name */
    fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 541cb3b..09cad24 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -297,18 +297,6 @@
    return SANDYBRIDGE_BCLK;
 }

-static void configure_mca(void)
-{
-	msr_t msr;
-	int i;
-	const unsigned int num_banks = mca_get_bank_count();
-
-	msr.lo = msr.hi = 0;
-	/* This should only be done on a cold boot */
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
-}
-
 static void model_206ax_report(void)
 {
    static const char *const mode[] = {"NOT ", ""};
@@ -340,7 +328,8 @@
 {

/* Clear out pending MCEs */
-	configure_mca();
+	/* This should only be done on a cold boot */
+	mca_clear_status();

/* Print infos */
    model_206ax_report();
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index 0773101..e0c2791 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -186,18 +186,8 @@
    }
 }

-static void mca_clear_errors(void)
-{
-	const unsigned int num_banks = mca_get_bank_count();
-	const msr_t msr = {.lo = 0, .hi = 0};
-
-	/* Zero all machine check error status registers */
-	for (unsigned int i = 0 ; i < num_banks ; i++)
-		wrmsr(IA32_MC_STATUS(i), msr);
-}
-
 void check_mca(void)
 {
    mca_check_all_banks();
-	mca_clear_errors();
+	mca_clear_status();
 }
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index a245824..9372513 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -336,17 +336,14 @@

void mca_configure(void)
 {
-	msr_t msr;
    int i;
    const unsigned int num_banks = mca_get_bank_count();

printk(BIOS_DEBUG, "Clearing out pending MCEs\n");

-	msr.lo = msr.hi = 0;
+	mca_clear_status();

for (i = 0; i < num_banks; i++) {
-		/* Clear the machine check status */
-		wrmsr(IA32_MC_STATUS(i), msr);
    	/* Initialize machine checks */
    	wrmsr(IA32_MC_CTL(i),
    		(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});