Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47864 )
Change subject: sb/intel/ibexpeak: Drop invalid SATA registers ......................................................................
sb/intel/ibexpeak: Drop invalid SATA registers
Code was copy-pasted from older chips and has no effect on ibexpeak.
Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/sata.c 2 files changed, 4 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47864/1
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 76d0ad6..94f927a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -154,48 +154,8 @@ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
-#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d148570..2c6b0ca 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -63,18 +63,8 @@ pci_write_config8(dev, INTR_LN, 0x0b);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL; // | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); @@ -137,18 +127,8 @@ pci_write_config8(dev, INTR_LN, 0xff);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* Port enable */ reg16 = pci_read_config16(dev, 0x92);
Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47864 )
Change subject: sb/intel/ibexpeak: Drop invalid SATA registers ......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/47864/comment/0fe840d1_3eda5116 PS3, Line 7: registers register settings?
(not all register writes are fully removed)
https://review.coreboot.org/c/coreboot/+/47864/comment/280ea585_00845c30 PS3, Line 7: invalid obsolete?
Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47864
to look at the new patch set (#4).
Change subject: sb/intel/ibexpeak: Drop obsolete SATA register settings ......................................................................
sb/intel/ibexpeak: Drop obsolete SATA register settings
Code was copy-pasted from older chips and has no effect on ibexpeak.
Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/sata.c 2 files changed, 4 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47864/4
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47864 )
Change subject: sb/intel/ibexpeak: Drop obsolete SATA register settings ......................................................................
sb/intel/ibexpeak: Drop obsolete SATA register settings
Code was copy-pasted from older chips and has no effect on ibexpeak.
Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/sata.c 2 files changed, 4 insertions(+), 64 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 76d0ad6..94f927a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -154,48 +154,8 @@ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
-#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d148570..2c6b0ca 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -63,18 +63,8 @@ pci_write_config8(dev, INTR_LN, 0x0b);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL; // | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); @@ -137,18 +127,8 @@ pci_write_config8(dev, INTR_LN, 0xff);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* Port enable */ reg16 = pci_read_config16(dev, 0x92);
-
Angel Pons (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)