Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, yuchi.chen@intel.com.
Hello Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), yuchi.chen@intel.com,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85153?usp=email
to look at the new patch set (#12).
Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
......................................................................
soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
1. Route IRQ for on-chip end-points only (e.g. 00:1f.4
i801_smbus)
IRQ routing for devices under root ports needs additional
swizzle per decided by root port configurations, which will
postponed to later till there is actual usage.
2. Route IRQ based on FSP programmed end-point device ID <->
PIRQ mapping.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Signed-off-by: Shuo Liu shuo.liu@intel.com
---
M src/soc/intel/xeon_sp/include/soc/irq.h
M src/soc/intel/xeon_sp/lpc_gen6.c
2 files changed, 52 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/85153/12
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Gerrit-MessageType: newpatchset
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Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Gerrit-Change-Number: 85153
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